LG FPD1570 Service Manual page 33

BLOCK DIAGRAM FOR MC68HC908BD
PTA0/PWM8
PTA1/PWM9
PTA2/PWM10 PORT
A
PTA3/PWM11
REG
PTA4/PWM12
PTA5/PWM13
PTA6/PWM14
PTA7/PWM15
PTB0/PWM0
PTB1/PWM1
PTB2/PWM2
PORT
PTB3/PWM3
B
REG
PTB4/PWM4
PTB5/PWM5
PTB6/PWM6
PTB7/PWM7
PTC0/ADC0
PTC1/ADC1
PORT
C
PTC2/ADC2
REG
PTC3/ADC3
PTC4/ADC4
PTC5/ADC5
*: +5V open-drain
**: +3.3V port
else: +5V port
EXTAL** XTAL**
DATA
DIR
REG
OSCILLATOR
AND DIVIDE
BY 4
CPU CONTROL
DATA
DIR
CPU REGISTERS
REG
INDEX REG H
COND CODE REG V 1 1
USB
DATA
DIR
REG
48K bytes
FLASHROM
VDD VDD3
VSS
RST
IRQ
CORE
TIMER
(COP)
ALU
68HC08 CPU
ACCUM
INDEX REG X
STACK POINTER
PROGRAM COUNTER
H I N Z C
1,024 bytes
RAM
Pulse
Width
Modulation
(PWM)
Multi-master
IIC
8-bit ADC
DDC12AB
/IIC
PTE0/SOG/TCH0
DATA
PORT
DIR
E
PTE1/HSYNCO
REG
REG
PTE2/VSYNCO
PTD0/D+**
PTD1/D-**
PTD2*/DDCSDA*
DATA PORT
PTD3*/DDCSCL*
DIR D
PTD4/CLAMP
REG REG
PTD5*/IICSCL*
PTD6*/IICSDA*
TIMER
HSYNC
SYNC
PROCESSOR
VSYNC