MSI MS-7512 User Manual page 60

tWR
W hen the Configuration DRAM Timing by SPD is set to [Manual], the field is
adjustable. It specifies the amount of delay (in clock cycles) that must elapse
after the completion of a valid write operation, before an active bank can be
precharged. This delay is required to guarantee that data in the write buffers
can be written to the memory cells before precharge occurs.
tWTR
W hen the Configuration DRAM Timing by SPD is set to [Manual], the field is
adjustable. This item controls the W rite Data In to Read Command Delay memory
timing. This constitutes the minimum number of clock cycles that must occur
between the last valid write operation and the next read command to the same
internal bank of the DDR device.
tRRD
W hen the Configuration DRAM Timing by SPD sets to [Manual], the field is
adjustable. Specifies the active-to-active delay of different banks.
tRTP
W hen the Configuration DRAM Timing by SPD sets to [Manual], time interval
between a read and a precharge command.
MEMORY-Z
Press <Enter> to enter the sub-menu and the following screen appears.
DIM M1/2/3/4 Memory SPD Information
Press <Enter> to enter the sub-menu and the following screen appears.
D I M M 1 / 2 / 3 / 4 M e m o r y S P D
Information
These items display the current status
of the current DIMM Memory speed in-
formation suc h as momory type, max
bandwidth, manufacture, part number,
serial number, SDRAM cycle time, DRAM
TCL, DRAM TRCD, DRAM TRP, DRAM
TRAS, DRAM TRFC, DRAM TWR, DRAM
TWTR, DRAM TRRD and DRAM TRTP.
They are read only.
BIOS Setup
3-21