Reference Voltage And A/D Converters; Input Latch And Pld Sync; Adc Clock Circuit - Philips EM7U LCOS Service Manual

REFERENCE VOLTAGE AND A/D CONVERTERS (Figure 53)
The BLEND_FDB signals are fed to a resistor matrix to set the DC reference voltage for the
A/D converters. The signals are buffered by Transistors 7189 and 7188 to add bias to the
Analog FBL_OSD signal. The output of the matrix is also added to the High and Low
Reference voltages. Regulator 7185 sets the Upper Reference voltage while 7187 sets the
Lower Reference voltage. The output of the A/D converter is clocked out by the
ADC_CLOCK signal to the TTL outputs. The signal is output on a 6-bit data line. The Red,
Green, and Blue circuits work the same as this one.
INPUT LATCH AND PLD SYNC (Figure 54)
One of the three latches that are used to clock data to the PLD is shown. The OTC_BLEND
(FBLK) and two bits of the Blue are fed to Latch 7102. This data is clocked out to the PLD by
the CLK_RET line. The reference *_FDB lines are output from the PLD to set the sample ref-
erence voltage as described earlier. The DIV_ADCLK and HSYNC_PLL sync lines are used
to set the CLK_RET and ADC_CLOCK signals.
ADC CLOCK CIRCUIT (Figure 55)
The DIV_ADCLK and HSYNC_PLL signals are fed to a Phase Comparator, 7287. The Phase
Comparator drives Transistor 7282, 7280, and 7281. This circuit sets the reference voltage
for the amplifiers in 7283. IC 7283, A, B, and C make up a phase oscillator circuit. The
Frequency of this circuit is set by the value of Capacitors 2282, 2283, 2284, and the voltage
applied to the circuit. The output of the Oscillator feeds a series of buffer amplifiers in 7288
to produce the ADC_CLOCK and CLK_RET signals.
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