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LVDS TRANSMITTER (Figure 42)
The 8-bit digital Y and UV signal is fed to the LVDS (Low Voltage Differential Signaling)
Transmitter, 7100. IC 7100 converts the parallel 16-bit signal to a serial data output. The
output of the LVDS is held at 345mV to prevent RFI (Radio Frequency Interference). There
are four data pairs and one clock pair. This circuit uses an 85MHz clock and is able to trans-
fer data up to 300 Mbytes per second. The LVDS data is then sent to the MSB (Main Scaler
Board) for further processing.
FIGURE 42 - LVDS TRANSMITTER
Page 42
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