Pioneer DJM-400 Service Manual page 84

Pioneer djm-400 dj mixer service manual
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1
A
No.
Pin Name
EMIF-ADDRESS
39
EA2
40
EA3
41
EA4
42
EA5
43
EA6
44
EA7
46
EA8
B
49
EA9
51
EA10
58
EA11
61
EA14
62
EA13
63
EA16
64
EA12
65
EA15
66
EA18
68
EA17
C
69
EA19
EMIF-DATA
75
ED6/GP1 [6]
76
ED7/GP1 [7]
79
ED4/GP1 [4]
80
ED5/GP1 [5]
81
ED3/GP1 [3]
82
ED2/GP1 [2]
83
ED1/GP1 [1]
84
ED0/GP1 [0]
D
MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)
GP0 [4](EXT_INT4)
1
/AMUTEIN1
14
AXR0 [1]/AXR1 [14]
18
AXR0 [0]/AXR1 [15]
88
AFSR1
89
ACLKR1
91
AXR0 [15]/AXR1 [0]
92
AXR0 [14]/AXR1 [1]
94
AXR0 [13]/AXR1 [2]
E
95
AXR0 [12]/AXR1 [3]
97
AXR0 [11]/AXR1 [4]
98
AXR0 [10]/AXR1 [5]
99
AXR0 [9]/AXR1 [6]
100
AXR0 [8]/AXR1 [7]
102
ACLKX1
105
AMUTE1
107
AFSX1
F
110
AHCLKX1
112
AHCLKR1
84
1
2
I/O
External address (word, half-word, and byte address)
O
The EMIF adjusts the address based on memory width:
Width
Pins
Address
8
19:2
17 through 0
The ED7 - ED0 pins are muxed with general-purpose input/output 1 (GP1) pins.
I/O
The EMIFDIS bit in the DEVCFG register controls the function of these muxed pins, EMIF is
default.
I/O
General-purpose input/output 0 pin 4 and external interrupt 4 (default) or McASP1 mute input.
McASP0 TX/RX data pin 1 or McASP1 TX/RX data pin 14
I/O
McASP0 TX/RX data pin 0 or McASP1 TX/RX data pin 15
I/O
McASP1 receive frame sync or left/right clock (LRCLK)
I/O
McASP1 receive bit clock
McASP0 TX/RX data pin 15 or McASP1 TX/RX data pin 0
McASP0 TX/RX data pin 14 or McASP1 TX/RX data pin 1
McASP0 TX/RX data pin 13 or McASP1 TX/RX data pin 2
McASP0 TX/RX data pin 12 or McASP1 TX/RX data pin 3
I/O
McASP0 TX/RX data pin 11 or McASP1 TX/RX data pin 4
McASP0 TX/RX data pin 10 or McASP1 TX/RX data pin 5
McASP0 TX/RX data pin 9 or McASP1 TX/RX data pin 6
McASP0 TX/RX data pin 8 or McASP1 TX/RX data pin 7
I/O
McASP1 transmit bit clock
McASP1 mute output
GP0 [13], along with GP0 [0] and AMUTE1, function as boot mode configuration pins at device
O
reset.
I/O
McASP1 transmit frame sync or left/right clock (LRCLK)
I/O
McASP1 transmit high-frequency master clock
I/O
McASP1 receive high-frequency master clock
DJM-400
2
3
Pin Function
3
4
4

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