Chapter 4. Continuous Availability And Manageability; Reliability; Designed For Reliability - IBM Power 570 Technical Overview And Introduction

Draft Document for Review September 2, 2008 5:05 pm
Continuous availability and
Chapter 4.
manageability
This chapter provides information about IBM Power Systems design features that help lower
the total cost of ownership (TCO). The advanced IBM RAS (Reliability, Availability, and
Service ability) technology allows the possibility to improve your architecture's TCO by
reducing unplanned down time.
IBM POWER6 processor-based systems have a number of new features that enable systems
to dynamically adjust when issues arise that threaten availability. Most notably, POWER6
processor-based systems introduce the POWER6 Processor Instruction Retry suite of tools,
which includes Processor Instruction Retry, Alternate Processor Recovery, Partition
Availability Prioritization, and Single Processor Checkstop. Taken together, in many failure
scenarios these features allow a POWER6 processor-based system to recover transparently
without an impact on a partition using a failing core.
This chapter includes several features that are based on the benefits available when using
AIX as the operating system. Support of these features when using Linux can vary.

4.1 Reliability

Highly reliable systems are built with highly reliable components. On IBM POWER6
processor-based systems, this basic principle is expanded upon with a clear design for
reliability architecture and methodology. A concentrated, systematic, architecture-based
approach is designed to improve overall system reliability with each successive generation of
system offerings.

4.1.1 Designed for reliability

Systems designed with fewer components and interconnects have fewer opportunities to fail.
Simple design choices such as integrating two processor cores on a single POWER chip can
dramatically reduce the opportunity for system failures. In this case, a 16-core server will
include half as many processor chips (and chip socket interfaces) as with a
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