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4.0 OPERATION
The M218 is a register-based instrument that is controlled through a series of I/O registers
described in Section 3.2.1. The exact method of accessing and addressing the I/O registers is
dependent on the M-Module carrier used to interface the module to your data acquisition or test
system. Refer to the carrier's documentation for information on the address mapping of an M-
Module's I/O registers and to your system software documentation for details on data access.
Typically a high level driver is available to aid in control of the module. Refer to the software
driver documentation for instructions on using the driver.
4.1 FIFO STRUCTURE
The FIFO (First-In-First-Out) structure allows multiple writes to the module to be stacked-up.
This helps reduce interrupt overhead by allowing an interrupt only after the completion of the last
relay operation in a sequence of up to eight operations. Eight was chosen because it allows at
least one open and one close to each of the four relay rows, allowing a complete change of all
relay states.
If the M-Module is enabled to interrupt, it asserts the INT line on the M-Module interface to the
Carrier when the last commanded relay operation in the FIFO has completed. For example, if
relays in only one row were instructed to move, the module asserts an interrupt after that one row
has been driven. If four rows were instructed to move (four writes to the FIFO--see note below),
then the module asserts an interrupt only after the completion of the fourth operation.
Note: The module asserts an interrupt after the relay drive time is complete (relay drive timer) and no
other operations have been stored in FIFO. The above example assumes the four writes are stored in
FIFO one after the other with very little time between the writes. If, in the above example, the
amount of time between writes is greater than the relay drive time (8 ms), the module would
actually interrupt four times--one interrupt after driving each relay.
4.2 RELAY SET/RESET
When the FIFO is empty (no relay operations pending) bits 03, 02, 01, and 00 in the above
registers indicate the state of the corresponding relay. Logic "1" means the relay in Row n
Column n is closed or soon will be (depending on the FIFO Empty Status bit's state). Logic "0"
means the corresponding relay is open. Following are some general notes on relay operation:
1. Writing to a Row n Set register closes the relays only in the bit positions set to logic
"1." Writing logic "0" to a Row n Set register has no effect on relay position. Writing
to a Row n Reset register opens relays only for the bit positions set to logic "0."
Writing logic "1" to a Row n Reset register has no effect on relay position.
2. Reading either the Row n Set or Row n Reset register addresses returns identical data
because they are actually mapped to the same register. When you write to one of these
registers (and FIFO is not full), the data is stored in the register and stored in FIFO.
C&H Technologies, Inc. <> 445 Round Rock West Drive <> Round Rock, Texas 78681 <> www.chtech.com
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