Sharp FO-5700 Service Manual page 52

FO-5700U
LZ9FJ59 (IC17) Terminal list
PIN I/O Name
1 IO2M RTCDT
2 O2M RTCCK
3 O2M RTCCE
4 O2M RTCIO
5 TO GAIN
6 I MTSTART
7 I LCINT
8 O2M XLCCS
9 O AO9
10 O AO10
11 – GND
12 O AO11
13 O AO12
14 O2M XLCRD
15 O2M XLCWR
16 O AO0
17 O AO1
18 O AO2
19 O AO3
20 – VDD
21 – GND
22 O AO4
23 O AO5
24 O AO6
25 O AO7
26 O AO8
27 O CRNT
28 – GND
29 O TXB1
30 O TXB0
31 O TXA1
32 O TXA0
33 O TXPB
34 O TXPA
35 I A12
36 I A11
37 I A10
38 I A9
39 I A8
40 – GND
41 ID QMPDRQ
42 O2M XQMPDAK
43 ID QMCDRQ
44 O2M XQMCDAK
45 O2M XQMRD
46 O2M XQMWR
47 O2M XQMCS
48 IO2M D15
49 IO2M D14
50 IO2M D13
Function
RTC data input/output
RTC data transfer clock
RTC chip select
RTC input/output control
Output port
Input port
Interrupt request signal from LC82103
Chip select signal to LC82103
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Ground
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Read signal to LC82103
Write signal to LC82103
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Power supply
Ground
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Reading/QM-coder LSI address output
Output port
Ground
B-phase current control output 1
B-phase current control output 0
A-phase current control output 1
A-phase current control output 0
B-phase current direction setting
A-phase current direction setting
System address input
System address input
System address input
System address input
System address input
Ground
DMA request input (QM-coder)
DMA acknowledge output (QM-coder)
DMA request input (QM-coder)
DMA acknowledge output (QM-coder)
Read signal to QM-coder
Write signal to QM-coder
Chip select signal to QM-coder
System data input/output
System data input/output
System data input/output
5 – 8
PIN I/O Name
51 IO2M D12
52 IO2M D11
53 IO2M D10
54 I A7
55 I A6
56 I A5
57 I A4
58 I A3
59 I A2
60 IS SHCK
61 – GND
62 – VDD
63 I A1
64 I A0
65 IO2M D9
66 IO2M D8
67 IO2M D7
68 IO2M D6
69 IO2M D5
70 IO2M D4
71 IO2M D3
72 IO2M D2
73 IO2M D1
74 IO2M D0
75 – GND
76 IS XRESET
77 O2M XINT7
78 O2M XINT4
79 O2M XWAIT
80 I XRAS
81 I A18
82 I A19
83 I A20
84 I A21
85 I XCS2
86 I XCS6
87 I XWRL
88 I XWRH
89 I XRD
90 I XDACK0
91 O2M XDREQ0
92 I XDACK1
93 O2M XDREQ1
94 O2M XGABCS
95 O2M XSRAMCS
96 O2M XPGMCS
97 I XMDMINT
98 O2M XMDMCS
99 O XMDMRST
100 – VDD
Function
System data input/output
System data input/output
System data input/output
System address input
System address input
System address input
System address input
System address input
System address input
Clock (19.6MHz) from CPU
Ground
Power supply
System address input
System address input
System data input/output
System data input/output
System data input/output
System data input/output
System data input/output
System data input/output
System data input/output
System data input/output
System data input/output
System data input/output
Ground
Reset signal
Interrrupt request signal to CPU
Interrrupt request signal to CPU
Wait request signal to CPU
Input RAS signal from CPU
System address input
System address input
System address input
System address input
Chip select 2 signal input
Chip select 6 signal input
System write (high-order byte) signal
System write (low-order byte) signal
System read signal
DMA acknowledge 0 input from CPU
DMA request 0 output to CPU
DMA acknowledge 1 input from CPU
DMA request 1 output to CPU
Chip select (gate array B)
Chip select (SRAM)
Chip select (ROM)
Interrupt request signal from Modem
Chip select (Modem)
Modem reset output
Power supply