Sharp FO-5700 Service Manual page 50

FO-5700U
The above functions are controlled by getting an access to the interface
memory in the modem through the data bus from CPU (IC27) of the
control PWB. The interface memory is composed of 32 8-bit registers,
and is controlled with the bank switch. Accordingly, the register is se-
lected by the register selection signals (RS4 to RS0) of 5 bits and chip
selection signal (CS). The major content controlled by these registers is
as follows.
1) Configuration register
Mode setting of V34, V17, V29, V27, G2, FSK and tone transmission.
2) Option register
Equalizing method of equalizer, carrier detection threshold, addition of
echo suppressor protect tone, and setting of transmission/reception
mode.
3) Others
G2AGC control, tone frequency setting, and so on.
Moreover, data is read from these registers through the data bus to
monitor the statuses of the modem such as tone detection, training pat-
tern detection and so on.
Next, transmission/reception operation is described.
During sending, the sent data is given from the control block to the mo-
dem through the data bus. Then, it is modulated and sent to LIU PWB
with SIGTX signal. During receiving, the received data is sent from LIU
PWB to the modem with SIGRX signal and is demodulated. Then, it is
sent to the control block with the data bus. The above operation is done
with the modem LSI (IC).
(4) Image signal process block
CIS
VIDEO
SIGNAL
The CIS is driven by the LSI (LC82103), and the output video signal
from the CIS is input into the LC82103 through the amplifying circuit.
The ADC and buffer are provided in the LC82103, and the digital image
processing is performed.
(5) Speaker amplifier
The speaker amplifier monitors the line under the on-hook mode, out-
puts the buzzer sound generated from the SH7021, ringer sound, DTMF
generated from the modem, and line sound.
(6) Reading process and mechanical control block
1) Mechanical control block
The mechanical control block is mainly composed of the gate array (A)
(IC17: LZ9FJ59) to control the following.
(a) Sending motor control
The revolution speed and timing of the sending motor are controlled to
output the control signals to the motor driver (IC7).
(b) End stamp and LED lamp control
On/off of the end stamp and LED lamp is controlled with the software.
(7) Gate array (A) block
This block is mainly composed of the gate array (A) (IC17: LZ9FJ59),
and has the following functions.
1
Mapper
Mapping is executed in the memory area of the memories, gate ar-
ray (B), modem, CODEC and reading process LSI (LC82103).
2
Mechanical control block
Refer to 1) Mechanical control block of 2-6 Reading and mechanical
control block.
3
IC interface for clock
Writing and reading to IC (IC30: SM8578BV) for clock is executed in
the clock-synchronous type serial transfer mode.
4
5 LIU control port
PC interface
•
Control of PC I/F Asic (FO-47IF)
5 – 6
AMPLIFIER
CIRCUIT
CLOCK
VREF+
VREF–
Fig. 2
LC82103
(IC6)