Sharp FO-5700 Service Manual page 47

SH7021 (IC27) Terminal descriptions
Terminal No.
Classification Code
(TFP-100B)
Bus control WAIT
RAS
CASH
CASL
RD
WRH
WRL
CS0~CS7
AH
HBS,
LBS
WR
DMAC DREQ0,
DREQ1
DACK0,
DACK1
16-bit TIOCA0,
integrated TIOCB0
timer pulse unit
(ITU)
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
TOCXA4,
TOCXB4
TCLKA~
TCLKD
Timing pattern TP15~
controller (TPC) TP0
Serial TxD0,
communication TxD1
nterface (SCI)
RxD0,
RxD1
SCK0,
SCK1
I/O port PA15~
PA0
PB15~
PB0
I/O
54 I Wait
52 O Low address strobe
47 O High-order column
address strobe
49 O Low-order column
address strobe
57 O Read
56 O High-order write
55 O Low-order write
46~49, O Chip select 0 thru 7
51~54
61 O Address hold
20 O Low-/high-order byte
56 strobe
55 O Write
66,68 I DMA transfer request
(Channels 0 and 1)
65,67 O DMA transfer request
receiving (Channels
0 and 1)
51, I/O ITU input
53 capture/output
conveyor (Channel 0)
62, I/O ITU input
64 capture/output
conveyor (Channel 1)
83, I/O ITU input
84 capture/output
conveyor (Channel 2)
85, I/O ITU input
86 capture/output
conveyor (Channel 3)
87, I/O ITU input
89 capture/output
conveyor (Channel 4)
90, O ITU output conveyor
91 (Channel 4)
65,66,90, I ITU timer clock input
91
100~93, O Timing pattern
91~89, Output 15 thru 0
87~83
94, O Sending data
96 (Channels 0 and 1
93, I Receiving data
95 (Channels 0 and 1)
97, I/O Serial clock
98 (Channels 0 and 1)
68~64, I/O Port A
62~60,
58~51
100~93, I/O Port B
91~89,
87~83
Name
It is input to insert Tw into the bus cycle during access to the
external space.
Timing signal of low address strobe of DRAM
Timing signal of column address strobe of DRAM
It is output for access to high-order 8 bits of data.
Timing signal of column address strobe of DRAM
It is output for access to low-order 8 bits of data.
It indicates that outside is read out.
It indicates writing at the external high-order 8 bits.
It indicates writing at the external low-order 8 bits.
Chip select signal for external memory or device
Address hold timing signal for device which uses multiplex bus of
address/data
Strobe signal of high/low byte
(Commonly used with AO, WRH.)
Output during writing. (Commonly used with WRL.)
Input terminal of DMA transfer request from external
It indicates that DMA transfer request is received.
Output terminal of input capture input/output conveyor
Output terminal of input capture input/output conveyor
Output terminal of input capture input/output conveyor
Output terminal of input capture input/output conveyor
Output terminal of input capture input/output conveyor
Output terminal of output conveyor
External clock input terminal to counter of ITU
Output terminal of timing pattern
Sending data output terminal of SCI0, 1
Receiving data input terminal of SCI0, 1
Clock input/output terminal of SCI0, 1
Input/output terminal of 16 bits
Input/output can be assigned for each bit.
Input/output terminal of 16 bits
Input/output can be assigned for each bit.
5 – 3
FO-5700U
Function