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82555 — Networking Silicon
Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed
circuit board layout and other design constraints.
3.1
Pin Types
Pin Type
I
O
I/O
B
3.2
Clock Pins
Symbol
X1
X2
3.3
Twisted Pair Ethernet (TPE) Pins
Symbol
TDP
TDN
RDP
RDN
3.4
Media Independent Interface (MII) Pins
Symbol
RXD3
RXD2
RXD1
RXD0
8
This type of pin is an input pin to the 82555.
This type of pin is an output pin from the 82555.
This type of pin is both an input and output pin for the 82555.
This pin is used as a bias pin. The bias pin is either pulled up or down with a resistor. The bias pin
may also be used as an external voltage reference.
Pin
Type
56
I
Crystal Input One. X1 and X2 can be driven by an external 25 MHz crystal.
Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator
when X2 is left floating. (The crystal should have a tolerance of 50 PPM or
better.)
55
O
Crystal Output Two. X1 and X2 can be driven by an external 25 MHz
crystal. Otherwise, X1 may be driven by an external MOS level 25 MHz
oscillator when this pin is left floating.
Pin
Type
47
O
Transmit Differential Pair. These pins send the serial bitstream for
transmission on an unshielded twisted pair (UTP) cable. The current-driven
48
differential driver can be two-level (10BASE-T or Manchester) or three-level
(100BASE-TX or MLT-3) signals depending on the operating mode. These
signals interface directly with an isolation transformer.
33
I
Receive Differential Pair. These pins receive the serial bitstream from the
isolation transformer. The bitstream can be two-level (10BASE-T or
34
manchester) or three-level (100BASE-TX or MLT-3) signals depending on the
operating mode.
Pin
Type
97
O
Receive Data. In 100 Mbps and 10 Mbps mode, data is transferred across
these four lines one nibble at a time.
96
95
92
Description
Name and Function
Name and Function
Name and Function
Datasheet
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