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Chapter 4 System Support
4.2
PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation
in this particular system. For detailed information regarding PCI bus operation, refer to
the PCI Local Bus Specification Revision 2.2.
These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some components such as the GMCH and ICH are organized as multiple
devices). A function is defined as the end source or target of the bus transaction. A device may
contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the GMCH/ICH chipset components and is not physically accessible. The
AGP bus that services the AGP slot is designated as PCI bus #1. As this system is designed for
simplicity of system management, the PCI buses are not available for expansion purposes.
82810E or 82815 GMCH Component
Mem. Cntlr.
Function
Hub Link I/F
Hub Link Bus
Hub Link I/F
PCI Bridge
Function
PCI
Bus #2
82559
Network
I/F Cntlr.
iPAQ 2.0 (ICH2) only.
iPAQ 1.0/1.2 (ICH) only.
Figure 4-1. PCI Bus Devices and Functions
4-2
Compaq iPAQ Series of Desktop Personal Computers
PCI
Direct AGP
Bus #0
Graphics
Controller
82801 ICH or ICH2 Component
PCI Bus #0
NIC
EIDE
I/F
Controller
Function
Function
Second Edition – February 2001
USB
SMBus
I/F
Controller
Function
Function
LPC
AC97
Bridge
Audio
Function
Function
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