Instruction Set - IBM EM78P312N Specification

EM78P312N
8-Bit Microcontroller

5.19 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅ ). In this case, the
execution takes two instruction cycles.
In case the instruction cycle specification is not suitable for certain applications, try to
modify the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) The following commands are executed within two instruction cycles; "JMP",
"CALL", "RET", "RETL", "RETI", including the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ", "DJZA") instructions. In addition, instructions that are written to the
program counter are executed within two instruction cycles.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/2.
Furthermore, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
0 0000
0 0000
0 0000
0 0000
0 0000
0 0000
0 0000
0 0000
0 0000
0 0000
0 0000
0
56 •
Hex
0000 0000 0000
0000 0001 0001
0000 0010 0002
0000 0011 0003
0000 0100 0004
0000 rrrr 000r
0001 0000 0010
0001 0001 0011
0001 0010 0012
0001 0011 0013
0001 0100 0014
0000 0001 rrrr 001r
Mnemonic Operation
NOP No Operation
DAA Decimal Adjust A
A → CONT
CONTW
0 → WDT, Stop
SLEP
oscillator
0 → WDT
WDTC
IOW R A → IOCR
ENI Enable Interrupt
DISI Disable Interrupt
[Top of Stack] → PC
RET
[Top of Stack] → PC,
RETI
Enable Interrupt
CONTR CONT → A
IOCR → A
IOR R
Product Specification (V1.0) 10.03.2006
(This specification is subject to change without further notice)
Status
Affected
None
C
None
T, P
T, P
1
None
None
None
None
None
None
1
None