Z80 Memory Management; Clocks; Dsp; Z80 Reset - Lexicon MPX 110 Service Manual

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EEPROM_DATA is pulled high through RP10, this signal must remain in a high logic state, this is so the
EEPROM SDA signal can pull this signal to a low logic level to generate an acknowledge pulse after the
reception of each byte.

Z80 MEMORY MANAGEMENT

Note that all address decoding RAM_EN/, ROM_EN/, ROM_A15/A16 is done within the Lexichip3. These
signals select Z80 access from ROM (code), RAM (parameters and variables) and ROM A15/A16 (bank
switching).

CLOCKS

This chip mode determines various system parameters: Host address decode map, masterclock frequency
and source, and zclock frequency and source. Given the desire to have an audio sample rate of 44.1KHz,
the Lexichip 3 crystal input is selected as 11.2896 MHz, the internal PLL bumps this up 4X to a Lexichip 3
master clock frequency of 45.1584 MHz. All other clocks, including ZCLK/ are derived from this Lexichip 3
master clock. The conversion clocks, FS, 64FS, and 256FS are derived from the 11.2896 MHz xtal. Notice
the Z80 is multiplexed clocks through U6p5&6 (4B7). U7 clocks while in reset, then ZCLK from L3 once L3
is initialized.

DSP

L3 takes samples at word clock rate from the Codec in I2S format on A/D_DATA. L3 converts I2S to byte
audio data and puts it out to the audio data memory U10, a 1Mx16 DRAM. The L3 is setup pass 1
byte/cycle to the DRAM or 3x8 to pass the 24bit sample (LXD [7:0]). Since the DRAM part has a 16bit data
bus, the high 8 bits are pulled high with resistor packs RP5&6. Once the data is stored in the DRAM, the L3
will store pointers (taps) and process up to 255 steps per word clock. The DSP function will add historical
samples from the taps to current samples according to the algorithm for the effect. The combined samples
Sheet 4:
The Z80 (U8), ROM (U4), SRAM (U5, incoming encoder buffer (U9), and outgoing latch (U2) represent the
MPX110 microprocessor control circuits. The Z80 and the L3 interact regularly to control the processing.
For example, when the Z80 passes data to the memory map address for ZREG2/ the data will be latched
on U2 by the clk signal CLT_REG/ generated by the Lexichip. Similarly, when the Z80 reads from the
memory map address for ZDEC2/, the L3 will generate ENC_READ/ which passes data to the Z80 data bus
via U9. U6, multiplexes init clocks and reset with ZCLK and ZRST from the L3.
The L3 also selects code and data space for the Z80 with signals ROM_EN/ and RAM_EN/. Further, the
ROM is banked switched with signals ROM_A15 and ROM_A16. This allows block of 32KB to be selected.
The 128kx8, 27c010, OTP EPROM, U4) holds the boot and the application code.
Running the Z80 at 9.0316MHz and using the zero wait states for ROM access we can accommodate a
ROM with an access time of 112nS or better. By inserting one wait state we can use a ROM with an access
time of 223nS or better.
8K x 8 SRAM (U5) can have a relatively slow access time, 80ns, and faster will operate with one wait state
with the Z80 running at 9 MHz.

Z80 RESET

In order to guaranty the data bus is tri-stated when the Lexichip 3 is released from reset, the Z80 must have
a clock present at its ZCLK input when the Z80 released from reset. This is accomplished by using a
74VCTT14 (U7), along with C24 (10pf) and R32 (47k) as a feedback oscillator. A 74HC157 (U6) is used to
select the ZCLK source from either the U7 oscillator or the Lexichip 3, and also gates the reset signal for
the Z80 during reset.
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