Sheet 2; Single-Ended To Differential Converter; Ak4528 Codec - Lexicon MPX 110 Service Manual

MPX 110 Service Manual
for the pre-emphasis function performed before the conversion process. C59 and C62 are the +V and -V
power supply bypass capacitors for U18.
An impedance of 75 Ohms is developed by R52 and R53 for the left and right outputs respectively. These
resistors also provide current limiting protection. The output 1/4" unbalanced phone jacks (J6 and J7) are
configured in such a way that, when only the right jack (J7) is connected, the left and right outputs are
summed together to provide a mono output. The left jack (J6) can support stereo headphones if the right
jack is not connected. The left channel appears on the tip and the right channel appears on the ring of a
stereo phone plug of this three-conductor 1/4" phone jack. C55 and C56 are provided for RFI suppression
at the outputs.
Although the output op amp can drive high-impedance (>100 Ohms) headphones, it is not designed for low
impedance headphones. For best results, use a headphone amp.

Sheet 2

This sheet shows the CODEC device (U19), the input signal DC bias circuitry (R78 and R79), the single-
ended to differential input amplifiers (U22), and the differential to single ended output amplifiers (U20).
Shown also are the various clock and control signals used by the CODEC.

SINGLE-ENDED TO DIFFERENTIAL CONVERTER

Each section of dual op-amp U22 is a unity gain-inverting amplifier. R84 and R85 fix gains at 0dB for the left
channel and R97 and R98 for the right channel. The non-inverting inputs of each amplifier are tied to analog
ground, creating a virtual ground at the junctions of the input and feedback resistors for each channel.
Signals IN_ LEFT and IN_ RIGHT from the previous page are AC coupled into these amplifiers by C90 and
C102. Each phase of the differential output signal pairs are impedance balanced via R82/R83 for the left
channel and R95/R96 for the right, and then AC coupled via C86/C87 and C96/C97 respectively. Each
phase of the differential signal pairs are then DC biased via the resistors R80/R81 and R93/R94. This DC
bias of 2.94V is provided by a resistive divider comprised of R78 and R79 while C82 and C83 de-couple
this bias voltage to remove ripple and noise. Because the CODEC samples the input at 256fs,
R82/R83/C65 and R95/R96/C66 form low pass filters. C86, C87, C96, and C97 simply provide AC coupling
into the CODEC.

AK4528 CODEC

The AKM CODEC AK4528 is a high performance 24-bit A/D-D/A device, which performs anti-alias filtering,
analog to digital conversion, and digital to analog conversion. Although it supports digital 15/50uS de-
emphasis and sampling rates up to 96kHz, the MPX110 uses analog de-emphasis and 44.1kHz sampling.
Digital de-emphasis is hardwired OFF (DEM0 =1, DEM1=0).
The Codec AINL/R inputs are fully differential. The input signal range is scaled to the VREF pin. Nominally,
this range is defined as (0.56 x VREF) Volts peak to peak. With VREF equal to 5V and a DC input offset
voltage of 2.9V The output code of the ADC is 0x7FFFFF positive full scale and 0x800000 negative full
scale. The data is in 2's complement form. The input is sampled at 64fs (2.8224 MHz with fs = 44.1kHz).
Serial data is clocked in on the rising edge of the bit clock and is aligned with the second bit clock following
the leading edge of each transition in the LRCLK (FS). This alignment is determined by setting the serial
data interface pins to support the I2S format. The Lexichip3 receive port (SDIN0) is configured to support
this format.
During power up and power down, the ADC, DAC, digital filters, and control registers are reset by signal
PWR_DN/. This is an active low signal and is provided by a latch, U2 (4C7). The CODEC is brought out of
power down mode when the Z80 writes ZD6=1 to Lexichip bit map address (xB2E) ZREG2/ latching
PWR_DN high and the ADC and DAC initializes after a period of LEX_256FS.
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