Differential To Single-Ended Output Amplifiers; Sheet 3; L3 Initialization - Lexicon MPX 110 Service Manual

The CODEC is constantly making ADC conversions of the AINL/R signals and output them in I2S format on
pin 13 SDTO, or A/D_DATA to the Lexichip (3B6). Similarly, the CODEC takes the D/A_DATA from the
Lexichip in on pin 14 SDTI in I2S format and the DAT presents balanced analog outputs at AOUTL/R+/-.
A quick test of A/D and D/A integrity can be accomplished by removing R59, lifting U19pin14 and
connecting U19p13 and U19p14. This bypasses all of the digital processing of the Z80 and Lexichip. In this
configuration, a sine wave on the input will equal the sin wave on the output with very little distortion. If
there is distortion or no signal out, then you know the problem is in the analog circuit. If this works fine, then
you know the problem is in the digital circuitry. (Of course, the effects' processing is out of the circuit in this
mode.) Remember to remove jumper from p13-p14 and reinstall R59 when you have completed the test.
C63 and C64 provide power supply de-coupling of the analog supply line and voltage reference of the
AK4528 while C69 de-couples the digital supply line and output buffer supply pins. R60 DC couples the
analog and digital supplies together while providing a measure of isolation of digital switching currents from
leaking back into the analog supply.
C67 and C68 de-couple the VCOM pin of the CODEC. This pin is the bias voltage of the ADC inputs and
the DAC outputs; this voltage is equal to VA/2.

DIFFERENTIAL TO SINGLE-ENDED OUTPUT AMPLIFIERS

The analog outputs of the CODEC are full differential with a full-scale swing of (0.54 x VREF) volts peak to
peak. This output signal is centered on 2.5V. Both sections of dual op amp U20 are configured as unity gain
second order low pass filters with an Fc = 93.2kHz. These filters provide summing of the differential signals
for each channel into single-ended signals. R70, R72-R76, C77-C79 comprise the low pass filter for the left
channel (OUT_LEFT) while R61,R64-R68, C70-C72 form the low pass filter for the right channel
(OUT_RIGHT). Both signals are referred back to page 1 to the Output and Mute circuitry. Regulated +/-5V
rails power these op amps.

Sheet 3

Lexichip-3B (U11) is a Lexicon proprietary audio DSP (digital signal processor) ASIC (application specific
IC). The L3 has multiple functions: I/O processing, clock generation, sample management (DSP).

L3 INITIALIZATION

Configuration pull ups and pull downs, RP2, RP9 (10K resistor networks) set the operating mode of the
Lexichip3 via the data bus ZD[7:0] when the RESET/ is released. The pull up/down value follows:
7
Value 0
Function CHIP_TRST
CHIP_TRST: The unidirectional output buffers are enabled for normal operation.
EXTMCX2: Source MCX2 (8X XTAL Frequency) from internal PLL..
EXTMC: Generate MC (Masterclock) Internally.
ZCLKSEL: Z80 ZCLK = PLL Clock Divided by 10 (ZCLK clock-tree output).
HADEC: Select Z80 Address Map 0 (More details below).
ADDRESS MAP 0
0000 - 3FFF
4000 - 4BFF
4C00 - 4FFF
5000 - 5FFF
6000 - 7FFF
8000 - FFFF
Upon the rising edge of RESET/, the Lexichip 3 reads ZD[7:0]. However, if the Z80 reset was the same
signal as the L3 reset, then the L3 would never see the configuration resistors, since the Z80 would have
ZD Bits
6 5
0 0
EXTMCX EXTM
16K Common ROM (ZDEC0/)
3K Lexichip3 Internal Decodes*
1K Expansion Area (ZDEC2/)
4K Common SRAM (ZDEC1/) (* note 3)
8K Bank-Swapped SRAM (1-16 Banks, 8KB - 128KB) (ZDEC1/)
32K Bank-Swapped ROM (1-16 Banks, 32KB - 512KB) (ZDEC0/)
4:2 1:0
010 00
ZCLKSEL HADEC
Lexicon
6-3