Chipset Features Setup; Dram Timing; Sdram Cycle Length; Dram Read Pipeline - IBM CI5VGM Series User Manual

Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing

SDRAM Cycle Length

DRAM Read Pipeline

Sustained 3T Write

Cache Rd+CPU Wt Pipeline

Cache Timing

Video BIOS Cacheable
System BIOS Cacheable
Memory Hole At 15MB-16MB
AGP Aperture Size
Cyrix M2 ADS# delay
Auto Detect DIMM/PCI Clk
Spread Spectrum
OnChip USB

USB Keyboard Support

DRAM Timing

The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
SDRAM Cycle Length
This field sets the length of each SDRAM cycle. By default, this field is
set to 3.
DRAM Read Pipeline
When enabled, this field supports pipelining of DRAM reads.
Sustained 3T Write
This field allows support for PBSRAM sustained 3T writes.
Cache Rd+CPU Wt Pipeline
When enabled, this item allows pipelining of cache reads and CPU
writes.
Cache Timing
This field sets the timing of the cache in the system. The options are fast
and fastest. By default, this field is set to fast.
CI5VGM User's Manual
Chapter 3 BIOS Configuration
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
: SDRAM 8ns CPU Warning Temperature
: SDRAM 8ns Current System Temp.
: SDRAM 8ns Current CPU Temp.
: 3 Current CPU Fan Speed
: Enabled Current Chassis Fan Speed
: Enabled VCORE :
: Disabled +12V :
: Fast -5V :-
: Enabled

Shutdown Temperature

: Disabled
: Disabled
: 64M
: Disabled
:
: Disabled
: Disabled ESC : Quit
F1 : Help
: Enabled F5 : Old Values
: Disabled F6 : Load BIOS Defaults
F7 : Load Setup Defaults
: 66 C/151 F
:
:
:
:
VCC3 :
+5V :
-12V :-
: 75 C/167 F
: Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color
51