Table of Contents
Advertisement
Operation
3. External FIFO Clock – (Option 2) This option allows a station-derived standard clock
rate to be used to clock data out of the FIFO. The externally supplied clock must be
equal to the average receive data rate.
4. Modulator Clock – (Option 3) Uses the modulator data rate clock as the output
clock and obviously requires that the modulator and demodulator data rate be
identical.
The Receive FIFO operation can be set from the front panel or remote control, and consists of
selecting the output clock source, and either the delay time desired in milliseconds or the number
of bits of delay. The processor computes the other value based on the one entered and the
current data rate. The modem processor also keeps track of and can display the current FIFO fill
percentage status. The FIFO sets the delay or number of bits selected upon activation and this
center value represents 100% FIFO fill. At any time the FIFO may contain from 0% to 200% of
the set value. The percentage fill can also represent the percentage of delay with respect to the
setting. For example if the buffer was set to 2 mS of delay and the fill is 150% this represents 3
mS of delay.
When the data rate is changed the modem maintains delay time constant, automatically changing
the number of bits stored in the buffer to compensate.
NOTE: When the number of bits of delay are very small, one bit may represent a large
percentage change (e.g. if the delay is only 4 bits, each bit represents 25%). The delay
may be set from 4 bits to 131,070 bits at any data rate, resulting in a delay ranging from
0.00081mS (4 bits at 4.92 Mbps) to over 42,000 mS (131,070 bits at 2400 bps).
An overrun occurs when a bit is clocked into the FIFO causing the fill to reach a full 200% of the
selected value. This causes flushing the upper half of the FIFO, restoring the fill to 100%, re-
centering the FIFO. The data flushed is lost and cannot be recovered.
An under-run occurs when the last bit is clocked out of the FIFO, emptying it. This also causes
re-centering of the FIFO by resetting the buffer pointers to the mid or 100% level, resending all
the data in the buffer. Both conditions result in a potential serious disruption of traffic.
When an under or over-run occurs an internal modem flag is set indicating that a re-center has
occurred. The front panel display shows "Slip" and FIFO fill data percentages read from the
remote port are negative numbers. This latched flag may be reset at the front panel or by writing
to the remote port FIFO parameter.
The FIFO may also be re-centered at any time on command from either the front panel or via the
remote control. At the front panel the command is <Dem: Status - Buffer> and pressing the "1"
key, then "Enter" to confirm. Pressing the "0" key on this parameter will clear the "Slip Status".
In "framed" communications the severity of the disruption can be minimized by setting the buffer
size in bits to multiples of the frame size. For example if the total frame size is 512 bits and the
buffer is set to a size of 1024 bits an under or over-run would result in the frame flags remaining
in the same location in the data stream. Note that frames will still be errored by the under or over-
run, but synchronization may not be lost. If a superframe structure is used it is likely that
synchronization will still be lost.
3.10 Built-in 1:1 Redundancy Mode Operation
The PSM-500 modem has a built-in 1:1 redundancy mode that allows two modems to be
connected together sharing connections, but with only one unit "on-line". The built-in software
provides automatic back-up protection should the on-line unit indicate a failure by switching to a
functioning off-line unit.
A diagram of the connections is shown in Section 2.3.6.
This is a very low cost method of achieving redundancy and because of the design has both
advantages and disadvantages:
Page 3-36
PSM-500/500L/500LT SCPC Satellite Modem
PSM-500/500L/500LT - Rev. 0.91
Advertisement
Table of Contents
