Demodulator - Datum Systems PSM-500 Installation And Operation Manual

M500 vsat/scpc satellite modem
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PSM-500/500L/500LT SCPC Satellite Modem
Note: As of the time of this manual the burst mode is a special factory request option and not
installed in standard modems.
The Modulator IF output can be routed to the Demodulator input using a built-in "IF Loop-back"
function. The loop-back path provides a 25 dB attenuator to avoid overloading the receive input.

1.2.2 Demodulator

The Modem Demodulator uses direct conversion techniques for recovery of data from an incoming
carrier, and therefore like the modulator does not use heterodyning, and has no internal IF signal or
processing. Referring to Figure 1-2, the input RF signal is first input to the receive AGC amplifier.
The AGC amplifier has a range of greater than 40 dB at any data rate, allowing inputs over that
range while still meeting performance criteria. The range is controlled in several steps depending on
the data rate extending over the range of –20 dBm at high data rates to –84 dBm at low data rates.
The proper AGC gain is digitally determined as that which produces an optimal output from the A/D
converters and is thus derived after the A/D converters.
The RF input is then demodulated using a "Costas Loop", phase locked loop demodulator where the
signal is split using a 90 degree hybrid into I and Q channels. In BPSK mode, the I channel carries
the data information and the Q channel represents the noise and carrier phase information in the
Costas loop. For QPSK operation, the I and Q channels each carry data information. The I and Q
channel "eye" signals are not available as in many other modems because the signal/data
representation at this point is still strictly digital for direct signal processing.
A receive synthesizer generates the demodulator local oscillator which is at the desired receive
carrier frequency. The synthesizer is tunable over the range of 50 to 90 MHz (or 950 to 1900 MHz in
the L-Band modems) and has two tuning components; the LO step synthesizer used to tune in steps
of 500 kHz, and a Direct Digital Synthesizer (DDS) component used to acquire and track the
received carrier. The DDS control has two tuning sources; (1) the digital Costas demodulation loop
phase detector used to track an already "locked" signal and (2) the processor control used to set the
carrier frequency and acquire new signals. The processor controls the acquisition search over a
programmable range from ±100 Hz to ±1.25 MHz.
The I and Q channel baseband outputs of the Costas Loop demodulator are converted to digital data
streams by parallel 12 bit D/A converters. The digital information is then filtered via a Datum
Systems' proprietary programmable digital filter. The filtered sample output is sent to the input of the
Forward Error Correction (FEC) process (either Viterbi convolutional, concatenated Reed-Solomon,
8PSK TCM rate 2/3, Turbo Codes or LDPC decoder) circuit. Multiple bits of the filtered A/D
converter are used for "soft decision" decoding in the FEC, providing an improvement in
performance over hard decision decoding.
The A/D output is also available to a special Digital Signal Processor (DSP), which is used to
examine the incoming signals for known energy patterns and acquire carriers significantly faster
than conventional sweep acquisition. This DSP controlled acquisition is especially useful at low data
rates and can improve over a typical sweep by more than 2 orders of magnitude.
The receive signal processing shown in Figure 1-2 serves the following multiple functions:
1. Generates the soft decision symbol information for input to the FEC.
2. Recovers the bit rate clock from the incoming signal.
3. Measures the Es/No of the received signal.
4. Generates the receive AGC signal to set the input stage gain.
The FEC decoders are contained on one or two adaptor cards plugged into the main board (all
except the TPC are contained with the adaptors FPGA), which is under control of the onboard
processor.
A differential decoder and INTELSAT / V.35 descrambler for the received data signal can be
individually enabled or disabled by the processor based on the current FEC and other settings. It is
no longer under control of the front panel or command interface. This configuration is held in the
PSM-500/500L/500LT - Rev. 0.91
Description
Page 1-9

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