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Description
nonvolatile EEPROM and does not have to be reconfigured on power-up. The resulting received
data and clock signals are sent to the interface assembly. Receive interface clocking can take
several forms as explained below.
1.2.3 Modem Bit Rate Timing
The Modulator and the Demodulator each have 4 possible sources for their bit rate timing.
The Modulator always outputs the Send Timing signal, but the source of this timing may be either:
1. An Internally generated bit rate NCO locked to the Internal Reference,
2. The Demodulator Receive Clock,
3. An External input at the data rate or
4. An external input on the Interface Terminal Timing input.
The modem's internal reference is a 2.0 parts per million clock oscillator, which is sufficiently
accurate for most applications. If system timing requirements dictate a better reference, the internal
oscillator may be phase locked to an external reference applied at the rear panel.
The Demodulator always outputs the Receive Timing signal. The receive demodulator clock derived
from the receive signal is synchronous with the Receive Data and is the normal source of the
receive timing. If the system requires a different clock (which still must be the same average rate as
the demodulator's receive clock) then provisions are made to buffer the data in a programmable
FIFO. The demodulator receive clock is always used to clock the data into the FIFO. The clock
output can be either:
1. The Demodulator Receive Clock,
2. The Modulator Clock
3. An internally generated bit rate NCO locked to the Internal Reference, or
4. An External FIFO Clock applied on the interface connector.
If the demodulator receive clock is selected then the FIFO itself is physically bypassed by switching
circuitry.
The internally generated bit rate NCO locked to the Internal Reference oscillator is settable to 40 bit
accuracy. That is 1 part in 10 to the 12 or 1 part per trillion.
The PSM-500 series includes two changes to previous modems to insure proper operation. First, the
modem detects if no data is present on the input by a lack of transitions for approximately 5 seconds
and will produce a programmable alarm after that time. Second, due to the higher data rates the
PSM-500 input circuitry automatically fine tunes the clocks to attempt to place the data period at the
optimal point with respect to the clocks. This also helps tremendously when using the TT clock to
create the transmit timing.
A block diagram simplified representation of the Transmit and Receive clock sources are shown in
Figure 1-3.
Page 1-10
PSM-500/500L/500LT SCPC Satellite Modem
PSM-500/500L/500LT - Rev. 0.91
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