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3. TECHNICAL BRIEF
3.8 Memory (U300)
The memory is consists of 128Mbit Nor Flash Memory and 32Mbit Pseudo SRAM. It has 16 bit
parallel data bus and 22 bit address.
Software, RF calibration data, audio parameters and battery calibration data are stored in the
Flash memory.
A-1 A0~A21
WP/ACC
RESET
CEf1
CEf2
RY/BYf
BYTE
CE1ps
CE2ps
A-1, A0 to A21
DQ0 to DQ15
, CE2ps
CE1ps
CEf1, CEf2
OE
WE
LB, UB
/ ACC
WP
RESET
BYTE
RY /
Vccps
Vccf
Vss
DU
NC
A-1 A0~A21
A0~A20
WE
OE
UB
LB
Figure 3-13. Block Diagram of Memory.
Table 3-8. Pin Description of U300.
Address inputs
Data inputs / outputs
Chip enable inputs for Pseudo SRAM
Chip enable inputs for Nor Flash Memory
Output enable input
Write enable input
Data byte control inputs for Pseudo SRAM
Write protect/program acceleration input for Nor Flash Memory
Hardware reset input for Nor Flash Memory
Word/Byte select input for Nor Flash Memory
Ready/Busy output for Nor Flash Memory
BYf
Power supply for Pseudo SRAM
Power supply for Nor Flash Memory
Ground
Don't use
Not connected
Vccf
Vss
DQ0~DQ15
(DQ0~DQ7)
128 Mbits
FLASH Memory
Vss
Vccps
328 Mbits
PSEUDO SRAM
DQ0~DQ15
- 28 -
DQ0~DQ15
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