I Nverter Operation - FSP Technology EP450 series Specifications

6 I nverter Operation

The Inverter circuit (Figure S-5) and PWM control are only active under Battery mode.
The Inverter circuit of Vesta is based on a full-Bridge circuitry and its output is driven by
a transistor which is controlled by CPU.
Refer to the Inverter circuit diagram, the CPU.M1, CPU.M2, CPU.M3, and CPU.M4 signals
are generated by CPU. Figure W-3 illustrates the waveforms of CPU.M1, CPU.M2, CPU.M3,
and CPU.M4 while the system is at no load condition. The duty cycles of CPU.M1, CPU.M2,
CPU.M3, and CPU.M4 signals are controlled by returned signal of output voltage (Please refer
to Charger circuit) to get a stable output.
The gates of MOSFETs are driven by transistors Q5, Q6, Q7, Q8, which are controlled by
the CPU.M1 M2.VGS M3.VGS and CPU.M4. Those signals are from CPU pin18, 19, 20 & 21
directly or indirectly. Figure W-3 (1) shows the collector waveforms for CPU pin18, 19, 20 and
21 while the system is at no load condition at battery mode.
These inverter transistors are turned on and off alternately to transfer DC voltage of battery to
an AC stepwave output voltage, and then magnifies through the transformer to generate
a stable 230VAC output.
According to the diagram shown on "Figure W-3 Control logic (1)", while the driving
signal M2.VGS and M3.VGS both get HI simultaneously in battery mode, the step output
waveform get approximately zero, which is named CLAMP. In full-bridge circuit,
unlike push-pull circuitry having isolated CLAMP circuitry and driven signal, the CLAMP signals
are included in inverter drive logic.
Page 13 of 26 Rev. A