Inputs And Outputs - Wavetek 39A Maintenance Manual

Zero Crossing Detector
IC201 is a comparator with positive feedback via R203. M is the signal selected by IC211 and M2
is the signals dc mid-point which is buffered by IC200-B. This circuit is used to detect zero
crossing of high frequency DDS waveforms of sine, ramp or triangle and sent to the FPGA.
Control DACs
IC27 is a 12-bit voltage output DAC with internal 2V reference. IC115 provides a bi-polar output of
± 3.3V. IC28 multiplexes the DAC output voltage onto the appropriate hold capacitor. FET input
amplifiers IC29 buffer the voltages on the hold capacitors.
IC208 is a quad 8-bit DAC. IC209D provides a 3.3V reference to give 0 to 3.3V DAC output.
IC209-A, -B and -C give gain and/or offset. VR200 gives coarse adjustment of the multiplier offset
and is only adjusted at initial calibration with the default calibration values present.
The voltage at each DAC output is controlled by the MPU which calculates each value from a
combination of the instrument set up and the calibration constants stored in EEPROM.
Reference Clock
IC105 is an integrated 10MHz voltage controlled crystal oscillator. If an external clock is applied,
C48 is charged up via D5 blocking the internal clock.
Phase-Locked-Loop and VCO
IC203 is a VCO tuned by varicap diodes D209-212. The range is 20MHz to 40MHz for square
and arbitrary waveforms and fixed at 27.48779MHz in the DDS mode. Comparator IC205 gives
TTL output levels.
IC206 is a PLL IC and has internal dividers for both inputs which are set by the MPU. Phase
comparison is done at 3kHz in PLL mode and slightly higher in DDS mode. IC15 is the loop filter
which drives the VCO. LED2 is out when the loop is in lock.

Inputs and Outputs

IC21 is a hex Schmitt; -A, -B, -D and -E are used for the Trig In and Hold In inputs. The Sync
output has four gates in parallel, IC202.
IC23 is an octal 3-state buffer. When Clock In/Out is an output the top four buffers are enabled
and the bottom four disabled. When Clock In/Out is an input the top four buffers are disabled and
the bottom four enabled.
The Zmod output high is set by the three digital signals at the input of IC16-A. IC16-A provides
gain to give a maximum output high of 14V. When Q14 is on, the output is low; when turned off
the output goes high until D2 conducts, clamping output high to the required level.
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