Wavetek 39A Maintenance Manual page 15

Clock Synthesis Mode
In Clock Synthesis mode the addresses are always sequential (an increment of one) and the
clock rate is adjusted by the user in the range 40MHz to 0.1Hz. The frequency of the waveform is
clock frequency ÷ waveform length, thus allowing short waveforms to be played out at higher
repetition rates than long waveforms, e.g. the maximum frequency of a 4 point waveform is
40e6÷4 or 10MHz but a 1000 point waveform has a maximum frequency of40e6÷1000 or 40kHz.
Arbitrary waveforms have a user defined length of 4 to 65536 points. Squarewaves use a fixed
length of 2 points and pulse and pulse train have their length defined by the user selected period
value.
DDS Mode
In DDS mode (Direct Digital Synthesis) all waveforms are stored in RAM as 4096 points. The
frequency of the output waveform is determined by the rate at which the RAM addresses are
changed. The address changes are generated as follows:
The RAM contains the amplitude values of all the individual points of one cycle (360º) of the
waveform; each sequential address change corresponds to a phase increment of the waveform of
360º/4096. Instead of using a counter to generate sequential RAM addresses, a phase
accumulator is used to increment the phase.
On each clock cycle the phase increment, which has been loaded into the phase increment
register by the CPU, is added to the current result in the phase accumulator; the 12 most
significant bits of the phase accumulator drive the lower 12 RAM address lines, the upper 4 RAM
address lines are held low. The output waveform frequency is now determined by the size of the
phase increment at each clock. If each increment is the same size then the output frequency is
constant; if it changes, the output frequency changes as in sweep mode.
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The generator uses a 38 bit accumulator and a clock frequency which is 2 x 10 (~27.4878
MHz); this yields a frequency resolution of 0.1 mHz.
Only the 12 most significant bits of the phase accumulator are used to address the RAM. At a
waveform frequency of F /4096 (~6.7MHz), the natural frequency, the RAM address increments
CLK
at every clock. At all frequencies below this (i.e. at smaller phase increments) one or more
addresses are output for more than one clock period because the phase increment is not big
enough to step the address at every clock. Similarly at frequencies above the natural frequency
the larger phase increment causes some addresses to be skipped, giving the effect of the stored
waveform being sampled; different points will be sampled on successive cycles of the waveform.
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