Wavetek 39A Maintenance Manual page 16

MPU and Memory
The majority of the digital hardware in the instrument is contained in 3 LSI devices, these being a
MicroProcessor Unit, IC3, and 2 Field Programmable Gate Arrays, IC10 and IC221.
The Z80180 MPU contains an 8 bit Z80 core, 2x16 bit counter-timers, 2x8 bit serial interfaces and
a memory management unit. The MPU is clocked at 12MHz by XTL1.
The MPU provides 20 memory address lines which are used to provide access to a total of 1M
bytes of memory, this comprising a 512k byte EPROM (IC4) and 5 128k byte rams IC5 – 9. The
EPROM is located at address 00000h and extends to 07FFFFh. The top 128k bytes are shared
by IC5 and the selection of ram or EPROM is controlled by the FPGA, IC10. The other 4 rams are
located at addresses 080000h to 0FFFFFh. IC9 is the system ram which contains all the essential
variables and work areas including the software stack. IC5 -8 is the non volatile store for all the
arbitrary waveforms and is not used for any other purpose. The MPU selects between the
memory devices via address decoders located in the FPGA at IC10.
The RS232 interface is provided directly by the MPU and is buffered to the rear panel connector
(PJ1) by IC1 and IC2.
One of the counter-timers provides a constant 0.5ms 'tick' to the MPU which is used to time all
the housekeeping functions, e.g. keyboard scan, knob control, as well as some generator
functions, e.g. frequency sweep. The second counter-timer is not used.
The FPGA, IC10, provides the port select signals to the GPIB board.
Keyboard, LCD and LEDs
The keyboard is interrogated every 10ms. This is done by reading the registers in IC12 and IC13.
If a key is down then one of the transistors Q6-Q13 will be on and the corresponding bits read
from IC12/IC13 will be high. The MPU decodes this to produce a key code which is passed to the
software. Multiple keys down are ignored. IC10 provides the port decode signals for access to
IC12 and IC13.
The knob is connected directly to the FPGA, IC10. This decodes the 4 states of the switches and
increments/decrements a counter. The counter is read and cleared every 10ms and the value and
sign passed to the software.
The 6 LEDs are driven directly from the outputs of IC18 and IC19 which are shift registers loaded
under CPU control by IC10.
The LCD is accessed via a bi-directional 4 bit port in IC10.
FPGA Waveform Generation
The FPGA, IC221, provides the complete waveform generation system including a 38-bit phase
accumulator (for DDS operation), a programmable divide-by-n register (for arbitrary waveform
playback), a 16-segment waveform sequencer, trigger/gate control logic, 20 bit re-loadable burst
counter, multi-instrument phase synchronisation logic and an 8-bit 16 port bi-directional MPU
interface.
Access is provided to the waveform RAM to allow the patterns to be written and the Sync and
Cursor/Marker output signals are generated.
All internal operations of the FPGA are clocked by the signal ARBCLK. Note that if this signal is
interrupted it is possible for the FPGA to become non-functional requiring the FPGA be
completely reset. The clock could be interrupted by a fault condition or by setting the CLOCK
BNC to INPUT and then providing an unacceptable clock. An unacceptable clock is any signal
which overrides the internal clock but produces a replacement which is less than 9MHz or greater
than 10.5MHz. This would happen if, for example, a DC voltage >2V was connected to the clock
input.
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