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Ziatech Corporation ZT 8903 Hardware User Manual

Single board 386 ex computer
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ZT 8903
ZT 8904
ZT 89CT04
Single Board 386 EX Computer
Hardware User Manual

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Summary of Contents for Ziatech Corporation ZT 8903

  • Page 1 ZT 8903 ZT 8904 ZT 89CT04 Single Board 386 EX Computer Hardware User Manual...

  • Page 2: Table Of Contents

    CONTENTS MANUAL ORGANIZATION ........................6 1. INTRODUCTION ..........................8 PRODUCT DEFINITION ......................8 ZT 8904..........................9 ZT 89CT04 ........................9 ZT 8903..........................9 STAND ALONE ......................9 STD 32 SINGLE MASTER....................9 STD 32 MULTIPLE MASTER..................9 FEATURES..........................10 DEVELOPMENT CONSIDERATIONS..................11 FUNCTIONAL BLOCKS ......................11 STD BUS INTERFACE ....................11 386 EX CPU .........................12 MEMORY AND I/O ADDRESSING ................13...
  • Page 3 Contents 4. INTERRUPT CONTROLLER ......................31 PROGRAMMABLE REGISTERS....................31 INTERRUPT ARCHITECTURE INITIALIZATION REGISTERS (ICW1-ICW4)....34 OPERATIONAL REGISTERS (OCW1-OCW3)..............36 STATUS REGISTERS (IRR, ISR, IPR) .................37 ADDITIONAL INFORMATION ....................38 5. COUNTER/TIMERS...........................39 PROGRAMMABLE REGISTERS....................41 COUNT REGISTERS AND COUNT LATCH ..............41 STATUS REGISTER ....................42 CONTROL REGISTER ....................43 ADDITIONAL INFORMATION ....................44 6.
  • Page 4 Contents PROGRAMMABLE REGISTERS....................78 BAUD RATE DIVISORS ....................78 DIVISOR LATCH LSB AND MSB..................79 INTERRUPT CONTROL REGISTER ................80 INTERRUPT STATUS REGISTER................81 LINE CONTROL REGISTER ..................82 LINE STATUS REGISTER....................83 MODEM CONTROL REGISTER...................83 MODEM STATUS REGISTER ..................84 ADDITIONAL INFORMATION ....................84 9. CENTRONICS PRINTER INTERFACE ....................85 PROGRAMMABLE REGISTERS....................85 LINE PRINTER DATA REGISTER ................85 LINE PRINTER STATUS REGISTER................85...
  • Page 5 Contents CONNECTOR DESCRIPTIONS .................123 CABLES ........................133 C. PIA SYSTEM SETUP CONSIDERATIONS ..................139 PREVENTING SYSTEM LATCHUP ..................139 POWER SUPPLY SEQUENCE MISMATCH ...............140 SIGNAL LEVEL MISMATCH..................142 PROTECTING CMOS INPUTS ....................143 RISE TIMES .......................143 INDUCTIVE COUPLING .....................144 ADDITIONAL INFORMATION ....................145 D. CUSTOMER SUPPORT........................146 TECHNICAL/SALES ASSISTANCE..................146 RELIABILITY...........................146 RETURNING FOR SERVICE ....................146...

  • Page 6: Manual Organization

    STD 32 architecture. All features of the ZT 8903 and ZT 8904 are the same, except that the ZT 8903 includes fewer features. The ZT 8903 is a more economical version of the ZT 8904 because of fewer features are included.
  • Page 7 Manual Organization Chapter 11, "System Registers", discusses the three system registers used to control and monitor a variety of functions on the ZT 8904. Chapter 12, "Watchdog Timer", lists the major features of the watchdog timer which monitors the ZT 8904 operation and takes corrective action if the system fails to function as programmed.

  • Page 8: Introduction

    -2 RS-232/485 Major Components PRODUCT DEFINITION The ZT 8904 family of products includes the ZT 8904, ZT 89CT04, and ZT 8903 products. The following topics describe these products. Using the ZT 8904 without the ® STD bus, as a single bus master, and as an STD 32 multiple master are also discussed.

  • Page 9: Zt 89Ct04

    ZT 8904 include the ZT 89CT04. ZT 8903 The ZT 8903 is a more economical board that includes all the features of the ZT 8904 except those listed below. Unless explicitly stated otherwise, all references in this manual to the ZT 8904 include the ZT 8903 as well.

  • Page 10: Features

    Additional AT peripherals include: Two RS-232 serial channels Two RS-232/485 DMA capable serial channels (not supported by ZT 8903) IEEE 1284 parallel port (Centronics, ECP, EPP) Optional IDE disk drive (not supported by ZT 8903) 24-point digital I/O with interrupt driven event sense and programmable debounce...

  • Page 11: Development Considerations

    In a multiple master system, up to seven ZT 8901, ZT 8902, or ZT 8904 boards share STD bus resources with a fixed or rotating priority granted by an external bus arbiter, such as the ZT 89CT39. The ZT 8903 does not support multiple master operation.

  • Page 12: Ex Cpu

    1. Introduction 386 EX CPU The ZT 8904 supports the Intel 386 EX CPU operating at 25 MHz. The 386 EX is a fully static 32-bit CPU core integrated with standard PC peripherals. Integrated peripherals include serial controller, interrupt controller, DMA controller, counter/timers, and watchdog timer.

  • Page 13: Memory And I/O Addressing

    128 Kbytes of battery-backed RAM. The battery-backed RAM is not available on the ZT 8903. System RAM can be expanded from 1 Mbyte to 5 Mbytes with the addition of an optional memory module. Memory operations up to 16 Mbytes that are not decoded by local memory devices are directed to the STD bus.

  • Page 14: Ieee 1284 Parallel Port

    D-shell connectors. The ZT 90200 cable provides the serial interface for the ZT 8904 and ZT 89CT04. The ZT 90203 cable provides the serial interface for the ZT 8903. A null-modem option is required to convert the DTE configuration to DCE.

  • Page 15: Timers

    1. Introduction Timers Three timers are included on the ZT 8904. Operating modes supported by the timers include interrupt on count, frequency divider, square wave generator, software triggered, hardware triggered, and one shot. The number of counter/timers available to the application programmer depends on the operating system. For example, the Ziatech MS DOS operating system uses timer 0 to generate system tick and timer 2 to control the speaker.

  • Page 16: Keyboard Controller

    1. Introduction Keyboard Controller ® The ZT 8904 includes a PC/AT keyboard controller that operates when the zVID local bus video adapter is installed. The keyboard connector is located on the zVID adapter. AC Power-Fail Protection With the addition of an AC transformer (connected to connector J3), the ZT 8904 monitors AC power to permit an orderly shutdown during a power failure.

  • Page 17: Getting Started

    STD 32 Bus Specification (ZT MSTD32) for STD bus applications. An STD 32 system is required for 16-bit data transfers to other STD bus boards and for multiple master operation. The ZT 8903 does not support multiple master operation.
  • Page 18 2. Getting Started Local RAM Drive - 8-bit battery-backed RAM (not available on the ZT 8903) paged for 128 Kbytes System BIOS - 16-bit pseudo static RAM shadowed from Flash #0 Extended RAM - Optional 16-bit pseudo static RAM module...

  • Page 19: I/O Configuration

    2. Getting Started RESERVED 180000h-3FFFFFh 140000h-17FFFFh FLASH #0 100000h-13FFFFh FLASH #1 STD BUS EXPANSION 080000h-0FFFFFh RESERVED 050000h-07FFFFh EXTENDED RAM 010000h-04FFFFh EXPANSION MODULE 00E000h-00FFFFh SYSTEM BIOS LOCAL RAM DRIVE 00D000h-00DFFFh STD BUS EXPANSION STD BUS EXPANSION 00C800h-00CFFFh 00C000h-00C7FFh VIDEO BIOS 00A000h-00BFFFh VIDEO RAM 000000h-009FFFh SYSTEM RAM...

  • Page 20: Connector Configuration

    2. Getting Started F900h-FFFFh AVAILABLE F800h-F8FFh CPU CONFIGURATION F500h-F7FFh AVAILABLE F4D0h-F4FFh CPU CONFIGURATION F4C0h-F4CFh WATCHDOG F400h-F4BFh CPU CONFIGURATION F100h-F3FFh AVAILABLE F000h-F0FFh CPU CONFIGURATION 0700-EFFFh AVAILABLE 0600h-06FFh RESERVED 0400-05FFh AVAILABLE 03F8h-03FFh COM1 03F6h-03F7h 03F0h-03F5h RESERVED 0300h-03EFh AVAILABLE 02F8h-02FFh COM2 02F0h-02F7h RESERVED 02E8h-02EFh COM4 02E0h-02E7h...

  • Page 21: Jumper Descriptions

    2. Getting Started J2 (FRONTPLANE INTERRUPT) J5 (MEMORY EXPANSION) J3 (AC POWER FAIL) J7 (POWER CONNECTOR) P/E (STD 32 INTERFACE) J6 (LOCAL BUS) J4 (PARALLEL I/O) J1 (SERIAL/PRINTER I/O) Connector Locations JUMPER DESCRIPTIONS The ZT 8904 includes several jumper options that tailor the operation of the board to specific application requirements.
  • Page 22 SETUP accepts only valid parameter sets: if changing one parameter invalidates another parameter, SETUP automatically updates the invalid parameter. After setting the parameters, press the F10 key to accept them. Ziatech Industrial BIOS Setup Utility Copyright (C) 2000, Ziatech Corporation 1.44M Floppy Disk A: ......Floppy Interface ......

  • Page 23: Std Bus Interface

    STD bus memory and I/O resources. This architecture is useful for applications that can be divided into modular control blocks, with each module running on a unique ZT 8904. The ZT 8903 does not support multiple master operation.  ...

  • Page 24: Std 32 Bus Compatibility

    3. STD Bus Interface STD 32 BUS COMPATIBILITY The ZT 8904 is compatible with Revision 1.2 of the STD 32 Bus Specification (Ziatech part number ZT MSTD32). Optional STD 32 features are discussed in terms of compliance levels. Permanent Master: SA16, SA8 - I, SDMABP, {MD} Temporary Master: SA16, SA8 - I, SDMABP, {MD} Compliance Levels The following is a brief description of the STD 32 compliance levels supported by the...

  • Page 25: Maskable Interrupts

    3. STD Bus Interface Maskable Interrupts The STD bus maskable interrupts monitored by the ZT 8904 are INTRQ* (P44), INTRQ1* (P37), INTRQ2* (P50), INTRQ3* (E67), and INTRQ4* (P5). These maskable interrupts are routed to a jumper configuration block (W17-22) for added flexibility. Note that an STD 32 backplane is needed to use INTRQ3*.

  • Page 26: Non-Maskable Interrupts

    3. STD Bus Interface In an edge-triggered architecture, multiple interrupt sources should not share the same interrupt request signal because it is possible to miss an interrupt request from one source while an interrupt request from another source is being serviced. For this architecture, each interrupt source requires a unique connection to the interrupt controller, as shown in the "STD Bus Vectored Interrupt...

  • Page 27: Reset

    RP16 and RP17. With both resistor packs installed, the ZT 8904 functions as a permanent master. With both resistor packs removed, the ZT 8904 functions as a temporary master. The ZT 8903 does not support multiple master operation.

  • Page 28: Intelligent I/O

    3. STD Bus Interface I / O S M E M L A V O R Y Z T 8 S L A 9 0 4 Z T 8 T E M P O R 9 0 4 M A S A R Y Z T 8 T E M...

  • Page 29: System Requirements

    3. STD Bus Interface I / O S M E M L A V O R Y Z T 8 S L A 8 3 2 Z T 8 I N T E L L 8 3 2 I G E Z T 8 I N T I / O...

  • Page 30: Multiple Master Reset

    3. STD Bus Interface An STD 32 backplane is required. The STD-80 backplane does not support the bus exchange protocol (DREQx* and DAKx*). A ZT 89CT39, or equivalent bus arbiter, is needed to manage ZT 8904 access to the STD bus resources. The arbitration may also be built directly on to the permanent master if a ZT 8904 is not used for this function.

  • Page 31: Interrupt Controller

    4. INTERRUPT CONTROLLER The ZT 8904 includes two Intel-compatible 8259 cascaded interrupt controllers that provide a programmable interface between interrupt-generating peripherals and the CPU. The interrupt controllers monitor 15 interrupts with programmable priority. When peripherals request service, the interrupt controller interrupts the CPU with a pointer to a service routine for the highest priority device.
  • Page 32 4. Interrupt Controller following table. The base address of the master interrupt controller is 20h and the base address of the slave interrupt controller is A0h. Interrupt Controller Register Addressing Address Register Operation Base+0h IRR, ISR, IPR Read Base+0h ICW1 Write Base+0h OCW2, OCW3...
  • Page 33 4. Interrupt Controller TIMER / COUNTER 0 STD BUS INTRQ1* KEYBOARD CONTROLLER SYSTEM REGISTER 3 (PORT 7D BIT 1) SERIAL PORT COM2 TO CPU SERIAL PORT COM1 MULTIPROCESSING STD BUS INTRQ4* J2 PIN 6 STD BUS INTRQ2* LOCAL FLOPPY SYSTEM REGISTER 0 (PORT 7B BIT 0) J2 PIN 8 1284 PARALLEL...

  • Page 34: Interrupt Architecture Initialization Registers (Icw1-Icw4)

    4. Interrupt Controller Interrupt Architecture Initialization Registers (ICW1-ICW4) Each interrupt controller must be initialized before it is used. Initialization consists of writing two, three, or four initialization commands. The programming sequence for these registers is given in the "Interrupt Initialization Programming"...
  • Page 35 4. Interrupt Controller Register: ICW2 Vector Address: Base+1 Access: Write Vector Pointer Upper 5 bits of pointer Initialization Register ICW2 Register: Master ICW3 Address: Base + 1 Access: Write Master Initialization Register ICW3 Register: Slave ICW3 Address: Base + 1 Access: Write Slave Initialization Register ICW3...

  • Page 36: Operational Registers (Ocw1-Ocw3)

    4. Interrupt Controller Operational Registers (OCW1-OCW3) The operation of each interrupt controller is managed by three 8-bit operational registers. These registers are programmed in any sequence for things such as enabling and disabling interrupt requests and changing interrupt priorities. Register: OCW1 Input Mask Address: Base + 1 Access: Read and Write...

  • Page 37: Status Registers (Irr, Isr, Ipr)

    4. Interrupt Controller Register: OCW3 SLCT Address: Base + 0 Access: Write Read Register 00 Do not use 01 Do not use 10 Select IR register 11 Select IS register Poll Command 0 No poll 1 Poll Mask Selection 00 Do not use 01 Do not use 10 Standard mask 11 Special mask...

  • Page 38: Additional Information

    4. Interrupt Controller Register: IPR Active Address: Base + 0 Access: Read Highest Active Request 000 IR0 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 Interrupt 0 No Interrupt present 1 Interrupt present Status Register IPR ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more information on the operating system's use of the interrupt inputs.

  • Page 39: Counter/Timers

    5. COUNTER/TIMERS The ZT 8904 includes one Intel-compatible 8254 device with a total of three programmable counter/timers. The counter/timers are useful for software timing loops, timed interrupts, and periodic interrupts. The major features of the counter/timers are listed below. Three 16-bit counter/timers Six programmable operating modes Binary and BCD counting Interrupt and polled operation...
  • Page 40 5. Counter/Timers The six programmable operating modes are summarized in the "Counter/Timer Operating Modes" table following. Counter/Timer Operating Modes Mode Counter/Timer Output Operation Transitions after programmed count expires Gate tied high to enable counting Transitions after programmed count expires Gate tied high to enable counting Periodic single pulse after programmed count expires Gate tied high to enable counting Square wave with frequency equal to programmed count...

  • Page 41: Programmable Registers

    5. Counter/Timers PROGRAMMABLE REGISTERS The counter/timers are accessed through four I/O addresses as shown in the following table. Each counter/timer occupies an I/O port address through which the preset count values are written and both the count and status information is read. The Control register occupies the remaining I/O port address, which services all three counter/timers.

  • Page 42: Status Register

    5. Counter/Timers Status Register Each counter/timer has a Status register. The Status register must be read using the multiple latch command specified in the Control register. Register: Status Access Mode OUTPUT NULCNT Address: 40h + Channel Access: Write Count Format 0 Binary 1 BCD Operating Mode...

  • Page 43: Control Register

    5. Counter/Timers Control Register The Control register is used to initialize the counter/timers and to select the method of reading the count and status information. The Control register is best described by dividing it into three formats as illustrated below. Register: General Control Select Access...

  • Page 44: Additional Information

    5. Counter/Timers Register: Multiple Latch Control STL CT2 Address: 43h Access: Write Counter Selection 001 Counter 0 010 Counter 1 100 Counter 2 Status Latch 0 Enabled 1 Disabled Control Latch 0 Enabled 1 Disabled Multiple Latch Control Register ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more information on the operating system's use of the counter/timers.

  • Page 45: Dma Controller

    6. DMA CONTROLLER The DMA controller used on the ZT 8904 is contained within the 386 EX microprocessor. It improves system operation by allowing external or internal peripherals to directly transfer data to or from ZT 8904 memory. The DMA controller can transfer data between memory and I/O with 8-bit or 16-bit data path widths.
  • Page 46 6. DMA Controller connections internal to the 386 EX. Note that the synchronous serial channel is not implemented on the ZT 8904 in favor of providing an additional asynchronous serial channel. Channel 0 supports the following devices as DRQ sources (DMACFG.6-4). External DMA slave request COM1 receive buffer full COM2 transmit buffer empty...

  • Page 47: Dma Implementation

    6. DMA Controller DMA IMPLEMENTATION The ZT 8904 DMA architecture external to the 386 EX is illustrated in the following figure, "DMA Architecture." The ZT 8904 supports a single DMA channel for STD bus DMA slaves. STD bus DMA slaves are I/O devices that use the ZT 8904 DMA channel 0 to transfer data between backplane I/O and ZT 8904 local memory.

  • Page 48: Dma Transfer Cycles

    6. DMA Controller U18C JPRX3 RESSM-04751 ICPSMCI-74FCT540Q U18B EOP/CT51 JPRX3 BUSRQ* / BRQ_DST DRQ0/DCD1 ICPSMCI-74FCT540Q ICPSMCI-7S32F / BUSAK DAK0/CS5 JPRX3 DRQ1/RXD1 LPT_DRQ DAK1/TXD1 RESSM-04751 JPRX3 / LPT_DAK ICP5MCI-386EX CT51 DCD1 RXD1 TXD1 DMA Architecture DMA TRANSFER CYCLES The ZT 8904 supports DMA channel 0 as a channel for backplane DMA slaves. Channel 0 must be programmed using two-cycle bus transfers.

  • Page 49: Programming A Dma Channel

    6. DMA Controller An external device or an internal peripheral requests service by activating a channel’s request input (DRQn). A requester in memory requests service through the DMA software request register. The requester either transfers data to or retrieves data from the target.

  • Page 50: Ex Dma Controller Registers

    6. DMA Controller 386 EX DMA CONTROLLER REGISTERS "386 EX DMA Controller Registers" table below lists the registers associated with the DMA controller. The following sections provide bit-level definitions for all registers associated with the DMA controller. Bit definitions in this section assume intended use of one or more DMA channels.

  • Page 51: Pin Mux Configuration

    6. DMA Controller DMA0TAR3 0F086h Channel 0 target address 24-25 DMA1TAR0 0F002h 0002h Channel 1 target address 0-7 DMA1TAR1 0F002h 0002h Channel 1 target address 8-15 DMA1TAR2 0F083h 0083h Channel 1 target address 16-23 DMA1TAR3 0F085h Channel 1 target address 24-25 DMA0BYC0 0F001h 0001h...
  • Page 52 6. DMA Controller D5 D4 D1 D0 REGISTER: PINCFG Pin mux configuration EXP ADDRESS: 0F826h AT ADDRESS: ACCESS: Must be written with a 1 Must be written with a 1 1= connect TXD1 to the package pin 0= connect /DACK1 to the package pin (required for DMA operation) 1= connect /CTS1 to the package pin 0= connect /EOP to the package pin (required for DMA operation) Must be written with a 0...

  • Page 53: Peripheral Connections And Mask

    6. DMA Controller Peripheral Connections and Mask The DMACFG register is used to select of the hardware DRQ sources for each channel and to mask the /DACKn signals at their pins when using internal requesters. D5 D4 D1 D0 REGISTER: DMACFG Peripheral connections and mask EXP ADDRESS:...
  • Page 54 6. DMA Controller D5 D4 D1 D0 REGISTER: DMA0REQ1 Channel 0 requestor address bits 8-15 ND ND ND ND ND ND ND ND EXP ADDRESS: 0F010h AT ADDRESS: R/W, BP = 1 ACCESS: Channel 0 requestor address bit 8 Channel 0 requestor address bit 9 Channel 0 requestor address bit 10 Channel 0 requestor address bit 11 Channel 0 requestor address bit 12...

  • Page 55: Channel 1 Requestor Address Registers

    6. DMA Controller Channel 1 Requestor Address Registers D5 D4 D1 D0 REGISTER: DMA1REQ0 Channel 1 requestor address bits 0-7 ND ND ND ND ND ND ND ND EXP ADDRESS: 0F012h AT ADDRESS: ACCESS: R/W, BP = 0 Channel 1 requestor address bit 0 Channel 1 requestor address bit 1 Channel 1 requestor address bit 2 Channel 1 requestor address bit 3...

  • Page 56: Channel 0 Target Address Registers

    6. DMA Controller D5 D4 D1 D0 REGISTER: DMA1REQ2 Channel 1 requestor address bits 16-23 ND ND ND ND ND ND ND ND EXP ADDRESS: 0F013h AT ADDRESS: ACCESS: R/W, BP = 0 Channel 1 requestor address bit 16 Channel 1 requestor address bit 17 Channel 1 requestor address bit 18 Channel 1 requestor address bit 19 Channel 1 requestor address bit 20...
  • Page 57 6. DMA Controller D5 D4 D1 D0 Channel 0 target address bits 8-15 REGISTER: DMA0TAR1 ND ND ND ND ND ND ND ND ADDRESS: 0F000h AT ADDRESS: 0000h R/W, BP = 1 ACCESS: Channel 0 target address bit 8 Channel 0 target address bit 9 Channel 0 target address bit 10 Channel 0 target address bit 11 Channel 0 target address bit 12...

  • Page 58: Channel 1 Target Address Registers

    6. DMA Controller Channel 1 Target Address Registers D5 D4 D1 D0 REGISTER: DMA1TAR0 Channel 1 target address bits 0-7 ND ND ND ND ND ND ND ND ADDRESS: 0F002h AT ADDRESS: 0002h ACCESS: R/W, BP = 0 Channel 1 target address bit 0 Channel 1 target address bit 1 Channel 1 target address bit 2 Channel 1 target address bit 3...

  • Page 59: Channel 0 Byte Count Registers

    6. DMA Controller D5 D4 D1 D0 REGISTER: DMA1TAR2 Channel 1 target address bits 16-23 ND ND ND ND ND ND ND ND ADDRESS: 0F083h AT ADDRESS: 0083h ACCESS: Channel 1 target address bit 16 Channel 1 target address bit 17 Channel 1 target address bit 18 Channel 1 target address bit 19 Channel 1 target address bit 20...
  • Page 60 6. DMA Controller D5 D4 D1 D0 Channel 0 byte count bits 8-15 REGISTER: DMA0BYC1 ND ND ND ND ND ND ND ND ADDRESS: 0F001h AT ADDRESS: 0001h ACCESS: R/W, BP = 1 Channel 0 byte count bit 8 Channel 0 byte count bit 9 Channel 0 byte count bit 10 Channel 0 byte count bit 11 Channel 0 byte count bit 12...

  • Page 61: Channel 1 Byte Count Registers

    6. DMA Controller Channel 1 Byte Count Registers D5 D4 D1 D0 Channel 1 byte count bits 0-7 REGISTER: DMA1BYC0 ND ND ND ND ND ND ND ND 0F0023 ADDRESS: AT ADDRESS: 0003h R/W, BP = 0 ACCESS: Channel 1 byte count bit 0 Channel 1 byte count bit 1 Channel 1 byte count bit 2 Channel 1 byte count bit 3...

  • Page 62: Dma Status Register

    6. DMA Controller D5 D4 D1 D0 Channel 1 byte count bits 16-23 REGISTER: DMA1BYC2 ND ND ND ND ND ND ND ND ADDRESS: 0F099h AT ADDRESS: ACCESS: Channel 1 byte count bit 16 Channel 1 byte count bit 17 Channel 1 byte count bit 18 Channel 1 byte count bit 19 Channel 1 byte count bit 20...

  • Page 63: Dma Command Registers

    6. DMA Controller DMA Command Registers The DMACMD1 resister is used to enable both channels and to select the rotating method for changing the bus priority control structure. Under all prioritization schemes, the DRAM refresh control unit receives highest priority. D5 D4 D1 D0 REGISTER:...

  • Page 64: Dma Mode Registers

    6. DMA Controller DMA Mode Registers The DMAMOD 1 register is used to select a particular channel's data-transfer mode and transfer direction, and to enable the channel's auto-initialize buffer-transfer mode. You can configure the DMA controller to modify the target address during a buffer transfer by clearing DMAMOD2.2, then use DMAMOD1.3 to specify how the channel modifies the address.

  • Page 65: Dma Software Request Register

    6. DMA Controller D5 D4 D1 D0 REGISTER: DMAMOD2 DMA mode register 2 ADDRESS: 0F01Bh AT ADDRESS: W/O, D0 specifies channel ACCESS: 1= Bits D7-D2 affect channel 1 0= Bits D7-D2 affect channel 0 Reserved 1= Channel target address hold 0= Channel target address will increment or decrement 1= Channel requestor address decrement 0= Channel requestor address increment...

  • Page 66: Dma Single Channel Mask Register

    6. DMA Controller DMA Single Channel Mask Register Use the DMAMSK register to enable or disable hardware requests for one channel at a time. D1 D0 REGISTER: DMAMSK DMA single channel mask register Reserved ADDRESS: 0F00Ah AT ADDRESS: 000Ah ACCESS: W/O, D0 specifies channel 1= Bit D2 affects channel 1 0= Bit D2 affects channel 0...

  • Page 67: Dma Chaining Register

    6. DMA Controller D5 D4 D1 D0 REGISTER: DMABSR DMA bus size register Reserved 0F018h ADDRESS: AT ADDRESS: ACCESS: W/O, D0 specifies channel 1= Bits D6 and D4 affect channel 1 0= Bits D6 and D4 affect channel 0 Reserved 1= Channel target bus width is 16 bits 0= Channel target bus with is 8 bits Reserved...

  • Page 68: Dma Interrupt Enable Register

    6. DMA Controller DMA Interrupt Enable Register The DMAIEN register is used to individually connect channel 0 and channel 1’s transfer complete signal to the ICU’s DMAINT interrupt request input. D5 D4 D1 D0 REGISTER: DMAIEN DMA interrupt enable register Reserved ADDRESS: 0F01Ch...

  • Page 69: Dma Overflow Enable Register

    6. DMA Controller DMA Overflow Enable Register Use DMAOVFE to specify whether all 26 bits or only the lower 16 bits of the target and requestor addresses are incremented or decremented during buffer transfers and whether all 24 bits of the byte count or only the lower 16 bits of the byte count are incremented or decremented during buffer transfers.

  • Page 70: Real-Time Clock

    7. REAL-TIME CLOCK ® The ZT 8904 includes one Motorola -compatible 146818 real-time clock. The real-time clock provides clock and 100-year calendar information in addition to 242 bytes of CMOS setup static RAM. These functions are battery backed for continuous operation even in the absence of system power.
  • Page 71 7. Real-Time Clock Real-Time Clock Register Addressing Address Function Range Offset Time-Seconds 0-59 Alarm-Seconds 0-59 Time-Minutes 0-59 Alarm-Minutes 0-59 Time-Hours (12 hour mode) 1-12 Time-Hours (24 hour mode) 0-23 Alarm-Hours 0-23 Day of Week Date of Month 1-31 Month 1-12 Year 0-99 Ah-Dh...

  • Page 72: Register A

    7. Real-Time Clock Register A Register: A Interrupt Rate Address: Offset+0Ah Access: Read and Write Rate Selection 0000 No Interrupts 0001 3.90625 ms 0010 7.8125 ms 0011 122.070 us 0100 244.141 us 0101 488.281 us 0110 976.562 us 0111 1.953125 ms 1000 3.90625 ms 1001 7.8125 ms 1010 15.625 ms...

  • Page 73: Register B

    7. Real-Time Clock Register B Register: B DM 24/12 DSE Address: Offset+0Bh Access: Read and Write Daylight Savings 0 Disabled 1 Enabled 24-hour/12-hour Operation 0 12-hour mode 1 24-hour mode Data Mode 0 BCD 1 Binary Update-End Interrupt 0 Disabled 1 Enabled Alarm Interrupt Enable 0 Disabled...

  • Page 74: Register D

    7. Real-Time Clock Register D Register: D Address: Offset+0Dh Access: Read Valid RAM 0 Invalid 1 Valid Register D ADDITIONAL INFORMATION Refer to the National Semiconductor PC87306 datasheet for more information on the real-time clock operating modes. The product folder for the PC87306, including the data sheet, is available on the web site http://www.national.com/pf/PC/PC87306.html.

  • Page 75: Serial Controller

    16450/8250, and two serial ports (COM3 and COM4) compatible with the 16550. The ZT 8903 includes only two serial ports, COM1 and COM2. The serial ports are implemented with a 5 V charge pump technology to eliminate the need for a ±12 V supply.

  • Page 76: Address Mapping

    8. Serial Controller Address Mapping The address mapping for the PC standard architecture and the ZT 8904 is shown below. Serial Channel PC Port Address ZT 8904 Port Address COM1 3F8-3FF 3F8-3FF COM2 2F8-2FF 2F8-2FF COM3 3E8-3EF 2E0-2E7 COM4 2E8-2EF 2E8-2EF Interrupt Selection The interrupt mapping for the PC standard architecture and the ZT 8904 is shown...

  • Page 77: Operation

    (J1). Optional cables convert the serial port interface to standard 9-pin D- shell connectors. The ZT 90200 cable provides the serial interface for the ZT 8904 and ZT 89CT04. The ZT 90203 provides the serial interface for the ZT 8903. The J1 connector pin assignments are given in the "J1 Peripheral...

  • Page 78: Programmable Registers

    8. Serial Controller PROGRAMMABLE REGISTERS Six registers are available for initializing and controlling each serial channel. The following table "Serial Controller Register Addressing" shows the I/O port addressing for the COM1 registers. The remaining serial channels are located as follows: COM2: 2F8-2FFh COM3:...

  • Page 79: Divisor Latch Lsb And Msb

    8. Serial Controller Baud Rate Divisors Baud Divisor Percent Rate (dec/hex) Error 2304/1440h 1536/960h 768/480h 384/240h 192/120h 1200 96/60h 1800 64/40h 2000 58/3Ah 0.69 2400 48/30h 3600 32/20h 4800 24/18h 7200 16/10h 9600 12/Ch 19200 6/6h 38400 3/3h 56000 2/2h 2.86 57600 2/2h...

  • Page 80: Interrupt Control Register

    8. Serial Controller Register: Divisor Latch MSB Address: 3F9h DIV=1 Access: Read and Write Divisor Latch MSB Interrupt Control Register Register: Interrupt Control Address: 3F9h DIV=0 Access: Read and Write Receive Buffer Interrupt 0 Disabled 1 Enabled Transmit Buffer Interrupt 0 Disabled 1 Enabled Line Status Interrupt...

  • Page 81: Interrupt Status Register

    8. Serial Controller Interrupt Status Register Register: Interrupt Status Source Address: 3FAh Access: Read Interrupt 0 Active 1 Inactive Interrupt Source 000 Modem Status Clear to send Data set ready Ring indicator Data carrier detect 001 Transmit Buffer 010 Receive Buffer 011 Line Status 110 Receive Fifo Timeout Break...

  • Page 82: Line Control Register

    8. Serial Controller Line Control Register Register: Line Control PTS PTE Address: 3FBh Length Access: Read and Write Character Length 00 5 bits 01 6 bits 10 7 bits 11 8 bits Stop Bits 0 1 bit 1 2.0 bits for Length = 6,7, or 8 1.5 bits for Length = 5 Parity Enable 0 No Parity...

  • Page 83: Line Status Register

    8. Serial Controller Line Status Register Register: Line Status TRB THR BRK FRM PTY OVR RBR Address: 3FDh Access: Read Receive Buffer 0 Empty 1 Full Overrun Error 0 No error 1 Error Parity Error 0 No error 1 Error Framing Error 0 No error 1 Error...

  • Page 84: Modem Status Register

    8. Serial Controller Modem Status Register Register: Modem Status Address: 3FEh DCD RIN DSR CTS DDD RIT DDR DCS Access: Read Delta Clear To Send 0 No transition 1 Transition Delta Data Set Ready 0 No transition 1 Transition Ring Indicator Trailing Edge 0 No trailing edge 1 Trailing edge Delta Data Carrier Detect...

  • Page 85: Centronics Printer Interface

    9. CENTRONICS PRINTER INTERFACE The bidirectional printer interface fully supports a Centronics-compatible printer. The Centronics interface is available through the J1 connector. Refer to the table "J1 Peripheral Pinout" in Appendix B for the connector pin assignments. PROGRAMMABLE REGISTERS The following topics illustrate the programmable registers for the Centronics printer interface.

  • Page 86: Line Printer Control Register

    9. Centronics Printer Interface Line Printer Control Register Register: Line Printer Control Address: 37Ah Access: Read and Write Data Strobe 0 Not asserted 1 Asserted Line Feed 0 No 1 Yes Initialize Printer 0 Reset 1 No reset Select Input 0 Off line 1 On line Interrupts...

  • Page 87: Parallel I/O

    10. PARALLEL I/O The ZT 8904 includes six 8-bit parallel ports for a total of 48 I/O signals. Three of the parallel ports are available to the application through frontplane connector J4. The remaining three parallel ports are dedicated to controlling and monitoring local operations.

  • Page 88: Output Latch

    10. Parallel I/O Passive Termination Connector J4 Internal Data Bus Output Data Latch Output Buffer Input Debounce Buffer Logic Event Detect Logic Parallel Port Functional Diagram Output Latch The output latch stores the data present on the internal data bus during a write operation to the parallel port.

  • Page 89: Input Buffer

    10. Parallel I/O Input Buffer The input buffer is enabled during read operations to transfer the data from connector J4 to the internal data bus. If the parallel port bit is configured as input, the data read is the data driven by an external device. The input buffer is an inverting device.

  • Page 90: 16C50A Enhanced Operating Mode

    10. Parallel I/O 16C50A Enhanced Operating Mode Enhanced operation adds extended event sense and input debounce capabilities. It is selected with four consecutive writes of 07h, 0Dh, 06h, and 12h to I/O port address 7Dh immediately after a power cycle or a reset. Three enhanced register banks are selected by programming bits 6 and 7 of I/O port 7Fh with a 00 for bank 0, a 01 for bank 1, and a 10 for bank 2.
  • Page 91 10. Parallel I/O Enhanced Bank 2 I/O Port Addressing Address Register Read Operation Write Operation 0078h Debounce Configure Status Control 0079h Debounce Duration Status Control 007Ah Reserved ----- ----- 007Bh Debounce Clock ----- Control 007Ch Reserved ----- ----- 007Dh Reserved ----- ----- 007Eh...
  • Page 92 10. Parallel I/O Register: Write Inhibit/Bank Address Mode: Enhanced (Bank 0) Port Port Port Bank Bank Address: 7Fh Access: Read and Write Port Write Inhibit 0 Inactive 1 Active Bank Address 00 Bank 0 01 Bank 1 10 Bank 2 11 Undefined Write Inhibit /Bank Address Register Note:...
  • Page 93 10. Parallel I/O Register: Event Sense Manage (Read) Mode: Enhanced (Bank 1) Port Port Port Address: 7Eh Global - Access: Read and Write Event Interrupt 0 Inactive 1 Active Global Interrupt 0 Inactive 1 Active Register: Event Sense Manage (Write) Mode: Enhanced (Bank 1) Port Port...
  • Page 94 10. Parallel I/O Register: Debounce Configure Mode: Enhanced (Bank 2) Port Port Port Address: 78h Access: Read and Write Debounce 0 Disable † 1 Enable Debounce Configure Register Note: This register controls whether each individual port or the external sense inputs are passed through the debounce logic before being recognized.
  • Page 95 10. Parallel I/O Register: Mask Mode: Enhanced (Bank 0) Bank Port Port Port Bank Address: 7Fh Access: Read and Write Port Write Inhibit 0 Inactive 1 Active Bank Address 00 Bank 0 01 Bank 1 10 Bank 2 11 Undefined Mask Register  ...

  • Page 96: System Registers

    11. SYSTEM REGISTERS Three system registers are used to control and monitor a variety of functions on the ZT 8904. These registers are implemented with the same Ziatech 16C50A ASIC that implements the 24 parallel I/O lines discussed in "Parallel I/O,"...
  • Page 97 11. System Registers LSI LSO STD PFL System Register 1 Permanent Master Operation 0 Temporary 1 Permanent Power Fail NMI 0 Active 1 Inactive STD Bus NMI 0 Active 1 Inactive Watchdog Timer NMI 0 Active 1 Inactive Local Bus Expansion 00 Type 0 01 Type 1 10 Type 2...

  • Page 98: Additional Information

    11. System Registers System Register 2 LED BDS VPP VMX C2S C1S KBD MIR Multiprocessing Interrupt 0 Active 1 Inactive Keyboard Interrupt 0 Local 1 System Com 1 Interface 0 RS 485 1 RS 232 Com 2 Interface 0 RS 485 1 RS 232 Video Mux 0 Enable...

  • Page 99: Watchdog Timer

    12. WATCHDOG TIMER The primary function of the watchdog timer is to monitor ZT 8904 operation and take corrective action if the system fails to function as programmed. The major features of the watchdog timer are listed below. Single-stage or two-stage operation Enabled and disabled through software control Armed and strobed through software control WATCHDOG TIMER OPERATION...

  • Page 100: Programmable Registers

    12. Watchdog Timer Stage 1 Latch Stage 1 (386EX) 1236A System Register 0 POR = 1 = RST 8MHz (7Bh, Bit 1) 100 Ms Minimum 400 Ms Typical 600 Ms Maximum Watchdog Timer Architecture PROGRAMMABLE REGISTERS The four register groups associated with the first stage of the watchdog timer are the following: Watchdog Timer Clear Watchdog Timer Status...

  • Page 101: Watchdog Timer Clear Register

    12. Watchdog Timer Watchdog Timer Clear Register The Watchdog Timer Clear register is programmed with a lockout sequence to enable watchdog timer mode and to reload the counter. The lockout sequence is shown below. Word write of F01Eh to F4C8h Word write of 0FE1h to F4C8h Register: Watchdog Clear Address: F4C8h...

  • Page 102: Watchdog Timer Counter Registers

    12. Watchdog Timer Watchdog Timer Counter Registers The Watchdog Timer Counter registers hold the current value of the down counter. Application software reads these registers to determine the current count value. A reload operation automatically transfers the contents of the Watchdog Reload registers to the Watchdog Timer registers.

  • Page 103: Watchdog Timer Reload Registers

    12. Watchdog Timer Watchdog Timer Reload Registers The Watchdog Timer Reload registers are programmed with two word operations to set the reload value. After a lockout sequence, these registers are write protected until after the next reset or power cycle. A reload operation automatically transfers the contents of the Watchdog Reload registers to the Watchdog Timer registers.

  • Page 104: Local Bus Video

    13. LOCAL BUS VIDEO The ZT 8904 includes a local bus interface to permit high speed peripherals direct access to the CPU bus. This bus operates synchronously at CPU speeds of 25 MHz. Ziatech offers zVID video adapters designed specifically for this local bus interface. These adapters give superior performance over STD bus video solutions by running with four times the data width and more than four times the operating frequency.

  • Page 105: Numeric Data Processor

    14. NUMERIC DATA PROCESSOR The ZT 8904 includes a socket at location U26 designed to accept an 80387 numeric data processor. The numeric data processor extends the CPU instruction set to include trigonometric, logarithmic, and exponential functions. Adding a numeric data processor increases the application performance by as much as 10% on Whetstone and Livermore benchmarks.

  • Page 106: Programmable Led

    15. PROGRAMMABLE LED The ZT 8904 includes two Light-Emitting Diodes (LEDs) located immediately below the board extractor. The green LED is for the optional IDE disk drive; the red LED is general purpose. The red LED is software programmable through the LED bit in System Register 2.
  • Page 107 15. Programmable LED ;------------------------------------------------------------- ; led_off turns off the led. ;------------------------------------------------------------- led_off: pushf input_7d al,not 80h 07dh,al popf  ...

  • Page 108: Ac Power Fail

    16. AC POWER FAIL The ZT 8904 supports AC power-fail detection as a means for giving the application advanced warning of an impending power failure. The advanced warning may be used by the application for performing operations such as saving critical data and entering a dormant state.

  • Page 109: Jumper Configurations

    A. JUMPER CONFIGURATIONS The ZT 8904 includes several options that tailor the operation of the board to requirements of specific applications. Options are made by installing and removing shorting receptacles (jumpers). JUMPER OPTIONS The ZT 8904 includes jumpers with two posts and jumpers with three posts. Jumpers having only two posts are labeled Wx, where x defines the jumper number (for example, W12).
  • Page 110 A. Jumper Configurations DOS Factory Default Configuration Customer Jumper Configuration  ...

  • Page 111: Jumper Descriptions

    A. Jumper Configurations Jumper Descriptions The following topics list the jumpers in numerical order and provide a detailed † description of each jumper. A dagger ( ) indicates the default jumper configuration. W1-7 Reserved for Ziatech use. Do not install these jumpers. Numeric Coprocessor - indicates the presence of a numeric coprocessor.
  • Page 112 RS-485 operation through System Register 2. If configured for RS-485, the following jumpers adjust the RS-485 architecture to a specific application. These jumpers do not apply to the ZT 8903. COM1 Duplex † Half duplex (two wire) Full Duplex (four wire) COM2 Duplex †...
  • Page 113 A. Jumper Configurations W17-22 Maskable Interrupts - assigns up to nine interrupt sources to the interrupt controller inputs. Each interrupt input has two possible sources selected by installing a jumper in position "a" or position "b." Other combinations are possible with wire wrap techniques. Interrupt inputs not used in the application must be masked in software.
  • Page 114 A. Jumper Configurations W24-27 CPU Configuration - connects external hardware functions to multiplexed CPU pins. The CPU multiplexes DMA channel 0 and DMA channel 1 with serial port COM2 signals. In short, if DMA channel 0 is used to support STD bus DMA (such as the Ziatech ZT 8954 floppy disk controller), Data Carrier Detect and Clear To Send are not available for COM2.
  • Page 115 RS-232 or RS-485 operation through System Register 2. If configured for RS-485, the following jumpers adjust the RS-485 architecture to a specific application. These jumpers do not apply to the ZT 8903. W28a W28b COM1 Transmit Enable †...

  • Page 116: Specifications

    Supply Voltage, AUX +V: Not used Supply Voltage, AUX -V: Not used Storage Temperature: -40° to +85° Celsius Operating Temperature: ZT 8903: 0° to +65° Celsius ZT 8904: 0° to +65° Celsius ZT 89CT04: -40° to +85° Celsius Non-Condensing Relative Humidity: <95% at 40°...

  • Page 117: Battery Backup Characteristics

    B. Specifications Battery Backup Characteristics Battery Voltage: Battery Capacity: 255 mAH Real-time clock requirements: 5 µA maximum (when Vcc is below acceptable operating limits) Real-time clock data retention: 5 years minimum, 10 years typical Electrochemical Construction: Poly-carbonmonofluoride STD-80 Compatibility The ZT 8904 is designed for use in an STD 32 backplane environment. While designed to be backward compatible with STD-80 systems, the ZT 8904 is not guaranteed to work in all system topologies.
  • Page 118 B. Specifications STD Bus Signal Loading, P Connector PIN (CIRCUIT SIDE) PIN (COMPONENT SIDE) OUTPUT DRIVE OUTPUT DRIVE INPUT LOAD INPUT LOAD MNEMONIC MNEMONIC +5 VDC +5 VDC DCPDN* VBAT (INTRQ4) D7/A13 [1] D3/A19 [1] D6/A22 [1] D2/A18 [1] D5/A21 [1] D1/A17 [1] D4/A20 [1] D0/A16 [1]...
  • Page 119 B. Specifications STD Bus Signal Loading, E Connector PIN (CIRCUIT SIDE) PIN (COMPONENT SIDE) OUTPUT DRIVE OUTPUT DRIVE INPUT LOAD INPUT LOAD MNEMONIC MNEMONIC LOCK* XA23 XA19 XA22 XA18 XA21 XA17 XA20 XA16 RSVD NOWS* +5 VDC +5 VDC DREQx* DAKx* MASTER16* AENx*...

  • Page 120: Mechanical Specifications

    B. Specifications MECHANICAL SPECIFICATIONS The following topics list mechanical specifications, including card dimensions and weight, connectors, and cables. Card Dimensions and Weight The ZT 8904 meets the STD-80 Series Bus Specification for all mechanical parameters. In a card cage with 0.625 inch spacing, the ZT 8904 requires one card slot with or without the zVID local bus video adapter installed.

  • Page 121: Connectors

    B. Specifications Connectors The ZT 8904 includes 9 connectors to interface to the STD bus and application specific devices. Connector positions are illustrated in the "Connector Locations" figure below. A description and pin map for each connector is given in the following topics. J2 (FRONTPLANE INTERRUPT) J5 (MEMORY EXPANSION) J3 (AC POWER FAIL)
  • Page 122 B. Specifications Viking S3VT68/5DE12 or equivalent for the card extender. The figure below, "P/E Connector Pinout," shows pin assignments for the E connector and the table "STD Bus Signal Loading, E Connector" shows signal assignments. STD 32 STD 32 (Component Side) (Solder Side) P/E Connector Pinout  ...

  • Page 123: Connector Descriptions

    B. Specifications Connector Descriptions Connector Function Peripheral Frontplane Interrupt AC Power Fail Parallel I/O Memory Expansion Local Bus Auxiliary Power Optional IDE Reserved J1 (Peripheral) J1 is a latching 80-pin (dual 40-pin) male transition connector with 0.05 inch contact spacing. The serial ports, 1284 parallel port, and an external battery connection are available through J1.
  • Page 124 B. Specifications J1 Peripheral Pinout (continued) Signal Type Description Signal Type Description COM3 RXD Receive Data In/Out Data 2 COM3 RTS Request To Send /SLIN Select To Printer COM3 TXD Transmit Data In/Out Data 3 COM3 CTS Clear To Send ------ Ground COM3 DTR...
  • Page 125 B. Specifications J2 (Frontplane Interrupt) J2 is a latching 10-pin (dual 5-pin) male transition connector with 0.1 inch contact spacing. Frontplane interrupts are available through this connector. The pin assignments are given in the “J2 Frontplane Interrupt Pinout” table below. The mating connector is a T&B Ansley #622-1030 or equivalent.
  • Page 126 B. Specifications J3 (AC Power Fail) J3 is a latching 2-pin male low-profile header with 0.1 inch contact spacing. The AC input signals for the optional power-fail detection feature are available through this connector. The pin assignments are given in the “J3 AC Power Fail Pinout” table following.
  • Page 127 B. Specifications J4 (Parallel I/O) J4 is a 50-pin (dual 25-pin) vertical male header with 0.1 inch contact spacing. The 24 general purpose parallel I/O signals are included in this connector. The pin assignments are given in the “J4 Parallel I/O Pinout” table following. The pin assignments are chosen for direct connection to an I/O module mounting rack, such as those offered by Ziatech and Opto 22.
  • Page 128 B. Specifications J5 (Memory Expansion) J5 is a 54-pin (dual 27-pin) socket with 0.1 inch contact spacing. J5 includes memory address, data, and control signals for supporting RAM memory expansion and Flash boot modules. The pin assignments are given in the "J5 Memory Expansion Pinout" table below.
  • Page 129 B. Specifications J6 (Local Bus) J6 is a 100-pin (dual 50-pin) vertical receptacle with 0.05 inch contact spacing. This connector includes the signals needed for a local bus interface. This interface is used by optional piggyback adapters, such as the Ziatech zVID video adapters. The pin assignments are given in the “J6 Local Bus Video Pinout”...
  • Page 130 B. Specifications J6 Local Bus Pinout (continued) Pin# Signal Type Description Pin# Signal Type Description CPU Address ------ Ground CPU Address /BE1 Byte Enable CPU Address /SLCT Module Select CPU Address /BE2 Byte Enable CPU Address /PRES Module Present ------ +5 Volts /BE3 Byte Enable...
  • Page 131 B. Specifications J7 (Auxiliary Power) J7 is a location for a 2-pin latching COMBICON connector with 0.2 inch contact spacing. J7 includes the power and ground connections needed to power the ZT 8904 when the STD bus connection is not used. The pin assignments are given in the following table, "J7 Auxiliary Power Pinout."...
  • Page 132 B. Specifications J8 (Optional IDE) J8 is an optional 44-pin (dual 22-pin) vertical receptacle with 2 mm contact spacing. An IDE interface is provided through this connector. The pin assignments are given in the "J8 Optional IDE Pinout" table below. The board connector is a SAMTEC STMM-122- 01-S-D-SM or equivalent.

  • Page 133: Cables

    B. Specifications J9 (Reserved) J9 is reserved for Ziatech test purposes. Cables The following cables are available from Ziatech Corporation. They are included here for those who wish to make their own cables: ZT 90072 Digital I/O Cable ZT 90166...
  • Page 134 B. Specifications 11" 9.5" MALES FEMALES 11" TB ANSLEY 622-1030 TB ANSLEY 10-Pin Female 622-09PMI 104891-8 (2 Places) 104892-8 w/ Polarization (4 Places) COM 4 9-Pin Male Terminating Covers Receptacle (4 Places) w/ Latch Notes: COM 3 1) On side of connector P1 heat dry permanently stamp the following text: 90200-0.
  • Page 135 B. Specifications " 1 1/2" RED WIRE PIN 1 PIN 2 PIN 1 1 - 4 FOR ABRASION PROTECTION WRAP WITH BRADY DAT-69 1" SINGATRON (1" X 6") CLEAR LABEL HEAT SHRINK TUBING DJ-002-B 1/2" DIAMETER - TRIM OFF WHITE PORTION 5P DIN CONNECTOR BLACK ALPHA FIT 221-1/2 OF LABEL...
  • Page 136 B. Specifications HIRSCHMANN #MAK 50 S (930172-517) FEMALE 5 PINS AT 180 DIN CONNECTOR 10" PIN 2 PIN 1 1 - 4 FOR ABRASION PROTECTION WRAP WITH BRADY DAT-69 1" (1" X 6") CLEAR LABEL - TRIM OFF WHITE PORTION 3"...
  • Page 137 B. Specifications FOR ABRASION PROTECTION WRAP WITH BRADY DAT-69 HIRSCHMANN #MAK 50 S (930172-517) (1" X 6") CLEAR LABEL FEMALE 5 PINS AT 180 DIN - TRIM OFF WHITE PORTION CONNECTOR OF LABEL (13 PLACES) 10" PIN 2 6" 6" 6"...
  • Page 138 70 - 25 Connect to 10-Pin Female for +5V, 58 - 19 71 - 13 no connection to 9-Pin Male (COM1-2) 59 - 7 Justify 6 Conductors toward Pin 1. ZT 90203 Dual Serial and Printer Cable for the ZT 8903  ...

  • Page 139: Pia System Setup Considerations

    C. PIA SYSTEM SETUP CONSIDERATIONS The 16C50A Parallel Interface Adapter (PIA) device used on the ZT 8904 is designed by Ziatech to offer bidirectional I/O signals with or without event sense capability. This device features low power, high speed, wide temperature operation achievable only by utilizing CMOS technology.

  • Page 140: Power Supply Sequence Mismatch

    C. PIA System Setup Considerations Power Supply Sequence Mismatch A common application is to interface to a 24-position ZT 2226, Opto 22, or equivalent I/O module rack. Vcc and ground are provided from the ZT 8904 through connector J4 with Vcc protected by a 1 A fuse. This application is illustrated in Figure 1 below. In this application, no power supply sequence mismatch exists because the power supplying the input circuitry within the PIA is applied before or at the same time as the power supplying the external signals.
  • Page 141 C. PIA System Setup Considerations One solution is to switch the external signals' power supply with an output that is controlled by the computer. In this manner, if the computer is off, so is the external power supply. This solution is illustrated in Figure 3 following. Custom ZT 8904 Application...

  • Page 142: Signal Level Mismatch

    C. PIA System Setup Considerations Signal Level Mismatch Power supplying the external signal in Figure 1 is always relative to the PIA input circuitry power because power is provided over the interface cable. Signal level mismatches will not occur and proper system operation will result. However, if separate power supplies are used, there are two predominant causes of signal level mismatches.

  • Page 143: Protecting Cmos Inputs

    C. PIA System Setup Considerations ZT 8904 24-Position 16C50A Custom Application Power External Supply Power Supply Interface Cable Figure 7. Computer and External Power Supply with Common Switch and Ground Correct Power Supply Sequence, Correct Signal Level Match PROTECTING CMOS INPUTS The most common causes of damaged inputs are: Slow rise times, resulting in a ground bounce within the chip Inductive coupling on I/O lines causing noise to be coupled into the chip, resulting in...

  • Page 144: Inductive Coupling

    C. PIA System Setup Considerations Typically, optical isolators are used to help remove electrical noise while providing for different grounds. Separate grounds are achieved through the use of an additional power supply for the optocoupler rather than using the computer's power supply. If the computer's power supply powers the optocouplers, electrical isolation is defeated.

  • Page 145: Additional Information

    C. PIA System Setup Considerations them to conduct and allowing the majority of energy to flow through them instead of through the diode clamps. The 39 pF capacitor, in conjunction with the ferrite bead, forms an additional low pass filter, and is entirely optional. The 1k pullup ensures adequate rise time on the signal.

  • Page 146: Customer Support

    D. CUSTOMER SUPPORT This appendix offers technical assistance and warranty information for this product, and also the necessary information should you need to return a Ziatech product. TECHNICAL/SALES ASSISTANCE If you have a technical question, please call Ziatech's Customer Support Service at the number below, or e-mail our technical support team at tech_support@ziatech.com.

  • Page 147: Ziatech Warranty

    D. Customer Support Once you have an RMA number, follow these steps to return your product to Ziatech: 1. Contact Ziatech for pricing if the warranty expired. 2. Supply a purchase order number for invoicing the repair if the warranty expired. 3.

  • Page 148: Trademarks

    ® is a registered trademark of Quantum Software Systems Ltd. ® STD 32 is a registered trademark of Ziatech Corporation. STD 32 STAR SYSTEM™ is a trademark of Ziatech Corporation. ® TransZorb is a registered trademark of General Semiconductor. ®...
  • Page 149 1050 Southwood Drive San Luis Obispo, CA 93401 USA Tel: (805) 541-0488 FAX: (805) 541-5088 E-Mail: tech_support@ziatech.com Internet: http://www.ziatech.com...

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