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Ziatech Corporation ZT 8906 Hardware Manual

Single board computer with pentium processor
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Ziatech Corporation ZT 8906 Hardware Manual

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  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 ® with Pentium Processor H A R D W A R E M A N U A L For ZT 8905 Revision A.3 For ZT 8906 Revision A.3 ZT M8905 September 9, 1997 102575 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 1050 Southwood Drive • San Luis Obispo, CA 93401 USA • Tel (805) 541-0488 • FAX (805) 541-5088 Central Regional Office Eastern Regional Office European Office 7700 Chevy Chase Drive, Suite 110-A 319 North Pottstown Pike, Suite 107 P.O. Box 110 Austin, TX 78752 USA Exton, Pennsylvania 19341 USA AC SON...
  • Page 4 ® with Pentium Processor H A R D W A R E M A N U A L For ZT 8905 Revision A.3 For ZT 8906 Revision A.3 ZT M8905 September 9, 1997 102575 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 5 QNX is a registered trademark of Quantum Software Systems Ltd. STD 32 is a registered trademark of Ziatech Corporation. STD 32 STAR SYSTEM is a trademark of Ziatech Corporation. UNIX is a registered trademark of AT&T Bell Laboratories. VRTX32 is a registered trademark of Ready Systems, Inc.
  • Page 6 Pentium Processor. The term ZT 8905 is used throughout this manual to reference both the ZT 8905 and the ZT 8906, except where otherwise noted. Specific differences between the two are explicitly stated. The following summarizes the focus of each major section in this manual.
  • Page 7 Chapter 13, "PCI Mezzanine Local Bus," introduces the features of the Peripheral Component Interconnect (PCI) local bus interface that provides a high speed path between the CPU and peripherals. Chapter 14, "Programmable LED," provides code for turning the LED on and off. Appendix A, "Board Configuration,"...

  • Page 8: Table Of Contents

    CONTENTS CHAPTER 1. INTRODUCTION ......................1 PRODUCT DEFINITION ......................1 Stand Alone ........................1 STD 32 Single Master ....................2 STD 32 Multiple Master (STAR SYSTEM) ..............2 FEATURES OF THE ZT 8905....................2 DEVELOPMENT CONSIDERATIONS..................3 FUNCTIONAL BLOCKS......................4 STD 32 Bus Interface ....................
  • Page 9 Contents STD 32 BUS COMPATIBILITY ....................22 Standard Architecture ....................22 Extended Architecture....................23 Multiprocessing ......................23 STD 32 Compliance Levels ..................23 STD BUS INTERRUPTS ......................24 Maskable Interrupts ....................24 Non-Maskable Interrupts .................... 26 RESET ............................. 26 MULTIPLE MASTER AND INTELLIGENT I/O................. 26 Multiple Master......................
  • Page 10 Contents Write Mode Register ....................53 DMA Extended Mode Register................... 53 Clear Byte Register ....................54 Clear Master Register ....................54 Clear Mask Register....................54 Write Mask Register....................54 DMA Page Register....................55 DMA Extended Page Register ................... 55 ADDITIONAL INFORMATION....................55 CHAPTER 7.
  • Page 11 Contents CHAPTER 11. SYSTEM REGISTERS ....................75 PROGRAMMABLE REGISTERS .................... 75 System Register 0....................... 75 System Register 1....................... 76 CHAPTER 12. WATCHDOG TIMER....................77 WATCHDOG TIMER OPERATION..................77 ADDITIONAL INFORMATION ....................77 CHAPTER 13. PCI MEZZANINE LOCAL BUS..................79 PCI OPERATION FREQUENCY ..................... 79 ADDITIONAL INFORMATION ....................
  • Page 12 Contents ZIATECH 5+5 WARRANTY ....................107 Five-Year Limited Warranty..................107 Special Extended Warranty Option ................108 Life Support Policy....................108 APPENDIX D. PCI CONFIGURATION SPACE MAP ................ 109 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 13 Contents Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 14 TABLES Pentium Processor Comparison......................5 Typical DRAM Configurations ......................12 Connector Assignments ........................15 Interrupt Controller Register Addressing ....................33 Counter/Timer Operating Modes......................42 Counter/Timer Register Addressing ..................... 42 Slave DMA I/O Port Addressing ......................49 DMA Page I/O Port Addressing......................49 DMA Extended Page (A24-31) I/O Port Addressing ................
  • Page 15 Tables Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 16 ILLUSTRATIONS Functional Block Diagram ........................4 J5 Multi-I/O Connector..........................8 Memory Address Map .......................... 13 I/O Address Map........................... 14 Connector Locations........................15, 97 Socket T6C Location ..........................16 BIOS SETUP Utility: Screen 1....................... 18, 84 BIOS SETUP Utility: Screen 2....................... 18, 84 STD Bus Polled Interrupt Structure ......................
  • Page 17 Illustrations Write Mode Register ..........................53 DMA Extended Mode Register ......................53 Clear Byte Register ..........................54 Clear Master Register ........................... 54 Clear Mask Register ..........................54 Write Mask Register ..........................54 DMA Page Register ..........................55 DMA Extended Page Register ......................55 Register A .............................

  • Page 18: Chapter 1. Introduction

    Chapter 2, "Getting Started." PRODUCT DEFINITION The term ZT 8905 is used throughout this manual to reference both the ZT 8905 and the ZT 8906, except where otherwise noted. Specific differences between the two are explicitly stated. Refer to Appendix B for specifications.

  • Page 19: Std 32 Single Master

    Chapter 1. Introduction STD 32 Single Master The ZT 8905 supports additional memory and I/O through the STD 32 bus. Both Standard Architecture (8- and 16-bit) and Extended Architecture (8-, 16-, and 32-bit) transfer types are dynamically supported through the STD 32 interface. Jumperless configuration of interrupt, DMA, and STD 32 bus memory and I/O space is configured through the BIOS SETUP utility.

  • Page 20: Development Considerations

    Chapter 1. Introduction • On-board high efficiency 3.3 V DC-DC converter • Push-button reset • Software programmable LED • DC power monitors (3.3 V and 5 V) • Compatible with the following software: MS-DOS®, OS/2®, UNIX®, QNX®, VRTX32®, Windows™ 3.1 and 3.11, Windows 95, and Windows NT •...

  • Page 21: Functional Blocks

    Chapter 1. Introduction FUNCTIONAL BLOCKS The "Functional Block Diagram" below illustrates the board's major functional blocks. The topics that follow provide overviews of the functional blocks. IDE Local Interrupt IEEE 1284 Hard Disk Inputs Parallel Port Keyboard Two 16C550 Four 32-Bit Controller Serial Ports DMA Channels...

  • Page 22: Std 32 Bus Interface

    Chapter 1. Introduction STD 32 Bus Interface The ZT 8905 operates in the STD 32 system. In an STD 32 system, data transfers are dynamically sized for either 8- or 16-bit Standard Architecture or 8-, 16-, or 32-bit Extended Architecture transfers. All STD-80 compatible memory and I/O boards are supported using 8-bit Standard Architecture transfers.

  • Page 23: Memory And I/O Addressing

    Chapter 1. Introduction Memory and I/O Addressing The ZT 8905 includes two 72-pin sockets that support up to 48 Mbytes of DRAM. The ZT 8905 also supports Flash memory soldered directly on the board. Memory operations that are not decoded for on-board DRAM are forwarded to the STD 32 bus.

  • Page 24: Interrupts

    Chapter 1. Introduction Interrupts Two enhanced 8259 style interrupt controllers provide a total of 15 interrupt inputs. Interrupt controller features include support for level-triggered and edge-triggered inputs, fixed and rotating priorities, and individual input masking. Interrupt sources include counter/timers, serial I/O, real-time clock, keyboard, printer, and multiple master communications.

  • Page 25: Real-Time Clock

    Chapter 1. Introduction Real-Time Clock The real-time clock performs timekeeping functions and includes 256 bytes of general-purpose battery-backed CMOS RAM. Timekeeping features include an alarm function, a maskable periodic interrupt, and a 100-year calendar. The system BIOS uses a portion of this RAM for BIOS SETUP information (see "ZT 8905 SETUP"...

  • Page 26: Speaker Interface

    Chapter 1. Introduction Speaker Interface The ZT 8905 supports an external AT-compatible speaker through the multi-I/O frontplane connector (illustrated on previous page). Optional IDE Interface The ZT 8905 can be ordered (Option D1) with an on-board IDE interface connector for connection to an IDE hard drive.
  • Page 27 Chapter 1. Introduction Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 28: Chapter 2. Getting Started

    CHAPTER 2. GETTING STARTED This chapter summarizes the information needed to make the ZT 8905 operational. You should read this chapter before attempting to use the board. UNPACKING Please check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and Ziatech for an insurance settlement.

  • Page 29: Memory Configuration

    Chapter 2. Getting Started MEMORY CONFIGURATION The ZT 8905 addresses up to 4 Gbytes of memory. The address space is divided between memory local to the board, memory located on the PCI expansion interface, and memory on the STD bus. Any memory not reserved or occupied by a local memory device (DRAM/Flash) or the STD bus is available for PCI bus expansion.

  • Page 30: I/O Configuration

    Chapter 2. Getting Started 4 Gbyte 40000000h-3FFFFFFFFh 1 Gbyte PCI / STD 32 4000000h-3FFFFFFFh 64 Mbyte † 800000h-3FFFFFFh DRAM / PCI / STD 32 8 Mbyte 100000h-7FFFFFh LOCAL DRAM 1 Mbyte E0000h-FFFFFh BIOS SHADOW 896 Kbyte PCI / STD 32 D8000h-DFFFFh 864 Kbyte PCI / STD 32...

  • Page 31: I/O Address Map

    Chapter 2. Getting Started 64 K PCI or STD 32 E000-FFFFh (IOEXP driven low for addresses FC00h-FFFFh) D000-DFFFh C000-CFFFh PCI Config 5000-BFFFh 4000-4FFFh STD 32 or PCI (set by VGA location) 400-3FFFh (878h = System Register 1) COM1 3F8-3FFh 3F0-3F7h Floppy / IDE Registers 3E0-3EFh STD 32 or PCI...

  • Page 32: Connector Configuration

    Chapter 2. Getting Started CONNECTOR CONFIGURATION As shown in the "Connector Locations" drawing below, the ZT 8905 includes several connectors to interface to application-specific devices. A brief description of each connector is given in the "Connector Assignments" table below. Please note the revision of the ZT 8905 that you are using. The table below is for boards that are Revision A and higher, which have different connector assignments than the Revision 0 board.

  • Page 33: Jumper Descriptions

    Chapter 2. Getting Started JUMPER DESCRIPTIONS The ZT 8905 includes a few jumper options for features that cannot be provided for through the SETUP utility. As shown in the "Socket T6C Location" figure below, the jumpers are all located underneath the EPROM/FLASH socket (this is the socket used for the alternate boot image). Note that this socket is not normally occupied, allowing the jumpers to be easily accessed.

  • Page 34: System Configuration Overview

    Chapter 2. Getting Started System Configuration Overview The Ziatech Industrial BIOS and MS-DOS operating system software is preprogrammed in the ZT 8905's on-board Flash memory. The BIOS includes embedded support to allow the ZT 8905 Flash memory to be used as a solid-state drive (SSD) in the MS-DOS environment. Ziatech also supplies SSD support for other popular operating systems such as Windows NT and QNX (contact Ziatech for SSD drivers for specific operating systems).
  • Page 35 Chapter 2. Getting Started Ziatech Industrial BIOS Setup Utility Copyright (C) 1997, Ziatech Corporation 1.44M Floppy Disk A: ......Floppy Interface ....... STD32 Floppy Disk B: ......IDE Interface ......STD32 COM1 Port ....... ONBOARD 2482 16 63 Fixed Disk 0: ...

  • Page 36: Operating System Installation

    Chapter 2. Getting Started Operating System Installation It may be necessary to install an operating system such as Windows NT or QNX on the ZT 8905 system. This section describes the generic OS installation process. For OS-specific information, refer to the documentation provided by the OS vendor. Note: if the installation requires a CD-ROM drive, the appropriate drivers must first be installed in order to access the CD-ROM drive.
  • Page 37 Chapter 2. Getting Started Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 38: Chapter 3. Std 32 Bus Interface

    ZT 8905. STD 32 BACKGROUND The STD-80 Series Bus Specification , developed in the early 1980s by Ziatech Corporation, defines the electrical, mechanical, and functional characteristics of an STD bus system based on the 8088 series of microprocessors.

  • Page 39: Interrupts

    Chapter 3. STD Bus Interface Interrupts The STD-80 Series Bus Specification defines a single interrupt signal, INTRQ* (P44). If STD bus maskable interrupts are used in the application, the ZT 8905 is configurable to receive INTRQ* and four optional interrupts: INTRQ1* (P37), INTRQ2* (P50), INTRQ3* (E67), and INTRQ4* (P6). STD bus peripheral boards must be capable of generating an interrupt on INTRQ1*, INTRQ2*, INTRQ3*, and INTRQ4* to use this feature.

  • Page 40: Extended Architecture

    Chapter 3. STD Bus Interface Extended Architecture Extended Architecture 8-, 16-, and 32-bit peripherals are referred to as EA8, EA16, and EA32, respectively. The ZT 8905 supports interfacing to all three data width types. The ZT 8905 dynamically senses the type of peripheral at the start of the backplane cycle and will scale the transfer to match the data width of the peripheral.

  • Page 41: Std Bus Interrupts

    Chapter 3. STD Bus Interface SDMA16, SDMA8 Supports 8-bit or 16-bit Standard Architecture DMA as defined in the STD 32 Bus Specification and Designer's Guide . Control signals are provided through the frontplane connector. SDMABP Supports Standard Architecture DMA using BUSRQ*/BUSAK* for request and acknowledge and the backplane DMA control signals DMAIOR*, DMAIOW*, and T-C.

  • Page 42: Std Bus Polled Interrupt Structure

    Chapter 3. STD Bus Interface STD BUS INTRQ* INTRQ* INTERRUPT ZT 8905 SOURCE 1 INTRQ* INTERRUPT SOURCE 2 INTRQ* INTERRUPT SOURCE N INTERRUPT STATUS PORT STD Bus Polled Interrupt Structure STD BUS INTRQ* INTRQ* INTERRUPT INTRQ1* Frontplane ZT 8905 SOURCE 1 Interrupts INTRQ2* INTRQ1*...

  • Page 43: Non-Maskable Interrupts

    Chapter 3. STD Bus Interface Non-Maskable Interrupts The ZT 8905 supports the STD 32 signal NMIRQ* for system errors (see the "Non-Maskable Interrupt Structure" illustration below). The NMIRQ* signal is maskable through port 61h, bit 3. Write a 0 to enable, or a 1 to disable HMI for bit 3 of port 61h. SYSTEM CHIPSETS PORT...

  • Page 44: Multiple Master

    Chapter 3. STD Bus Interface Multiple Master A multiple master architecture requires one permanent master and one or more temporary masters, as illustrated in the "Multiple Master Architecture" figure below. The ZT 8905 is configurable for either permanent or temporary master operation. Each master has complete access to STD bus resources and operates at full speed when the local CPU is communicating with local memory and I/O.

  • Page 45: Multiple Master Vs. Intelligent I/O

    Chapter 3. STD Bus Interface I / O S M E M L A V O R Y Z T 8 8 3 2 S L A Z T 8 I N T E L L 8 3 2 I G E Z T 8 I N T I / O...

  • Page 46: Socket T6C Location

    Chapter 3. STD Bus Interface is also used to pull up the EA control signals that are open collector. Only one master in the system can provide these pullups. Normally, RP1 will be removed when configured as a temporary master (RP2 and RP3 removed).

  • Page 47: Multiple Master Reset

    Chapter 3. STD Bus Interface Multiple Master Reset In a multiple master system, a ZT 8905 configured as a permanent master operates the same as a ZT 8905 operating in a single master architecture. The permanent master monitors Vcc with a precision voltage monitoring circuit and holds the system in reset when Vcc is below 4.75 V.

  • Page 48: Chapter 4. Interrupt Controller

    CHAPTER 4. INTERRUPT CONTROLLER The ZT 8905 includes two Intel-compatible 8259 cascaded interrupt controllers that provide a programmable interface between interrupt-generating peripherals and the CPU. The interrupt controllers monitor 15 interrupts with programmable priority. When peripherals request service, the interrupt controller interrupts the CPU with a pointer to a service routine for the highest priority device. The major features of the interrupt architecture are listed below.

  • Page 49: Interrupt Architecture

    Chapter 4. Interrupt Controller TIMER / COUNTER 0 STD 32 INTRQ1* † ONBOARD KEY- BOARD CONTROLLER ONBOARD COM2 † STD 32 INTRQ* STD 32 INTRQ1* † STD 32 INTRQ2* J5 PIN2 ONBOARD COM1 † PENTIUM STD 32 INTRQ* STD 32 INTRQ1* †...

  • Page 50: Interrupt Sources

    Chapter 4. Interrupt Controller INTERRUPT SOURCES The interrupt sources are summarized below. Backplane: There are five STD bus interrupts routed to the interrupt configuration selection logic: INTRQ*, INTRQ1*, INTRQ2*, INTRQ3*, and INTRQ4*. These interrupts are active-low on the STD bus and inverted before they reach the interrupt configuration logic. Frontplane: Two of the five frontplane interrupts are routed to the interrupt configuration logic.

  • Page 51: Initialization Registers (Icw1-Icw4)

    Chapter 4. Interrupt Controller Initialization Registers (ICW1-ICW4) Each interrupt controller must be initialized before it is used. Initialization consists of writing two, three, or four initialization commands. The programming sequence for these registers is given in the "Interrupt Initialization Programming" figure. ICW1, ICW2, and ICW3 must be programmed during each initialization sequence.

  • Page 52: Initialization Register Icw1

    Chapter 4. Interrupt Controller Initialization Register ICW1 Register : ICW1 LTIM Address: Base+1 Access:Write Initialize ICW4 0 Disabled 1 Enabled Input Trigger 0 Edge Triggered 1 Level triggered Initialization Register ICW1 Initialization Register ICW2 Register: ICW2 Vector Address: Base+1 Access: Write Vector Pointer Upper 5 bits of pointer Initialization Register ICW2...

  • Page 53: Initialization Register Icw4

    Chapter 4. Interrupt Controller Initialization Register ICW4 Register: ICW4 AEOI SFNM Address: Base+1 Access:Write End of interrupt 0 Normal 1 Automatic Nesting mode 0 Standard 1 Special Initialization Register ICW4 Operational Registers (OCW1-OCW3) The operation of each interrupt controller is managed by three 8-bit operational registers. These registers are programmed in any sequence for things such as enabling and disabling interrupt requests and changing interrupt priorities.

  • Page 54: Operational Register Ocw2

    Chapter 4. Interrupt Controller Operational Register OCW2 Register: OCW2 Mode Level Address: Base + 0 Access: Write Interrupt level 000 IR0 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 Operational mode End of Interrupt 001 Non-specific 011 Specific Automatic Rotation...

  • Page 55: Operational Register Ocw3

    Chapter 4. Interrupt Controller Operational Register OCW3 Register: OCW3 SLCT Address: Base + 0 Access: Write Read Register 00 Do not use 01 Do not use 10 Select IR register 11 Select IS register Poll Command 0 No poll 1 Poll Mask Selection 00 Do not use 01 Do not use...

  • Page 56: Status Register Isr

    Chapter 4. Interrupt Controller Status Register ISR Register: ISR Service Address: Base + 0 Access: Read Input In Service 0 No 1 Yes Status Register ISR Status Register IPR Register: IPR Active Address: Base + 0 Access: Read Highest Active Request 000 IR0 001 IR1 010 IR2...

  • Page 57: Extended Mode Register

    Chapter 4. Interrupt Controller Extended Mode Register Register:EMR Master Address: 4D0h Slave Address: 4D1h Access: Read/Write IR0 (8) 0 = Edge triggered 1 = Level triggered IR1 (9) 0 = Edge triggered 1 = Level triggered IR2 (10) 0 = Edge triggered 1 = Level triggered IR3 (11) 0 = Edge triggered...

  • Page 58: Chapter 5. Counter/Timers

    CHAPTER 5. COUNTER/TIMERS The ZT 8905 includes one Intel-compatible 8254 device with a total of three programmable counter/timers. The counter/timers are useful for software timing loops, timed interrupts, and periodic interrupts. The major features of the counter/timers are listed below. •...

  • Page 59: Programmable Registers

    Chapter 5. Counter/Timers Counter/Timer Operating Modes Mode Counter/Timer Output Operation Transitions after programmed count expires. Gate tied high to enable counting. Transitions after programmed count expires. Gate tied high to enable counting. Periodic single pulse after programmed count expires. Gate tied high to enable counting Square wave with frequency equal to programmed count.

  • Page 60: Status Register

    Chapter 5. Counter/Timers Register: Count High High Byte Address: 40h + Channel Access: Read and Write Count Register High Byte Register: Count Low Low Byte Address: 40h + Channel Access: Read and Write Count Register Low Byte Status Register Each counter/timer has a Status Register. The Status Register must be read using the multiple latch command specified in the Multiple Latch Control Register (see end of this chapter).

  • Page 61: Control Register

    Chapter 5. Counter/Timers Control Register The Control register is used to initialize the counter/timers and to select the method of reading the count and status information. The Control register is best described by dividing it into three formats as illustrated in the following figures. General Control Register Register: General Control Select...

  • Page 62: Multiple Latch Control Register

    Chapter 5. Counter/Timers Multiple Latch Control Register Register: Multiple Latch Control Address: 40h Access: Write Counter Selection 001 Counter 0 010 Counter 1 100 Counter 2 Status Latch 0 Enabled 1 Disabled Control Latch 0 Enabled 1 Disabled Multiple Latch Control Register ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more information on the operating system's use of the counter/timers.
  • Page 63 Chapter 5. Counter/Timers Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 64: Chapter 6. Dma Controller

    CHAPTER 6. DMA CONTROLLER This chapter provides an overview of ZT 8905 DMA architecture and DMA controller operation. Descriptions of DMA controller programmable registers are also included. ZT 8905 SPECIFICS The ZT 8905 includes two cascaded, Intel-compatible, 8237 Direct Memory Access controllers that provide a programmable interface for direct transfers between peripherals and main memory.

  • Page 65: Programmable Registers

    Chapter 6. DMA Controller STD 32 BACKPLANE DRQ2 (DEFAULT FOR STD 32 FLOPPY DISK BUSRQ* CONTROLLER SUPPORT) DRQ5 BIOS SETUP CONFIGURABLE DACK2* BUSAK* DACK5* IEEE 1284 PARALLEL PORT ECP DRQ DRQ0 ECP DACK* DACK0* J5 MULTI I/O DRQ1 J5 PIN 52 DRQ* DACK1 J5 PIN 54 DACK* J5 PIN 51 DRQ*...

  • Page 66: Slave Dma I/O Port Addressing

    Chapter 6. DMA Controller Slave DMA I/O Port Addressing Address Slave Master Register Operation Channel 0 Base/Current Address Write Channel 0 Current Address Read Channel 0 Base/Current Count Write Channel 0 Current Count Read Channel 1 Base/Current Address Write Channel 1 Current Address Read Channel 1 Base/Current Count Write...

  • Page 67: Address Register

    Chapter 6. DMA Controller Address Register Register: Address Address Access: Read and Write A13 A12 Address Register (8-bit I/O) When programming a DMA channel configured for 16-bit I/O, the address is shifted as shown below. Register: Address † Address Access: Read and Write Address Register (16-bit I/O) †...

  • Page 68: Status Register

    Chapter 6. DMA Controller Status Register Register: Status Slave Address: 8 Master Address: D0 Access: Read Channel 0 TC 0 No 1 Yes Channel 1 TC 0 No 1 Yes Channel 2 TC 0 No 1 Yes Channel 3 TC 0 No 1 Yes Channel 0 Request...

  • Page 69: Write Request Register

    Chapter 6. DMA Controller Write Request Register Register: Write Request Slave Address: 9 Master Address: D2 Access: Write Request Channel Number 00 Channel 0 01 Channel 1 10 Channel 2 11 Channel 3 Request 0 Reset 1 Set Write Request Register Write Single Mask Register Register: Single Mask Slave Address: A...

  • Page 70: Write Mode Register

    Chapter 6. DMA Controller Write Mode Register Register: Write Mode Slave Address: B Master Address D6 Access: Write Mode Channel 00 Channel 0 01 Channel 1 10 Channel 2 11 Channel 3 Transfer 00 Verify 01 Write 10 Read 11 Do not use Autoinitialize 0 Disable 1 Enable...

  • Page 71: Clear Byte Register

    Chapter 6. DMA Controller Clear Byte Register Register: Clear Byte Slave Address: C Master Address: D8 Access: Write Clear Byte Register Clear Master Register Register: Clear Master Slave Address: D Master Address: DA Access: Write Clear Master Register Clear Mask Register Register: Clear Mask Slave Address: E Master Address: DC...

  • Page 72: Dma Page Register

    Chapter 6. DMA Controller DMA Page Register Register: DMA Page Address Access: Read and Write DMA Page Register † See the "DMA Page I/O Port Addressing" table earlier in this chapter. DMA Extended Page Register Register: DMA Extended Page Address Access: Read and Write DMA Extended Page Register...
  • Page 73 Chapter 6. DMA Controller Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 74: Chapter 7. Real-Time Clock

    CHAPTER 7. REAL-TIME CLOCK The ZT 8905 includes one Motorola-compatible 146818 real-time clock. The real-time clock provides clock and 100-year calendar information in addition to 242 bytes of CMOS setup static RAM. These functions are battery backed for continuous operation even in the absence of system power. The RAM is used by the operating system BIOS to store configuration information.

  • Page 75: Register A

    Chapter 7. Real-Time Clock Register A Register: A Address: Offset+0Ah Interrupt Rate Access: Read and Write Rate Selection 0000 No Interrupts 0001 3.90625 ms 0010 7.8125 ms 0011 122.070 us 0100 244.141 us 0101 488.281 us 0110 976.562 us 0111 1.953125 ms 1000 3.90625 ms 1001 7.8125 ms 1010 15.625 ms...

  • Page 76: Register C

    Chapter 7. Real-Time Clock Register C Register: C Address: Offset+0Ch IRQF Access: Read Update Flag 0 No update 1 Update Alarm Flag 0 No alarm 1 Alarm Periodic Interrupt Flag 0 No interrupt 1 Interrupt Interrupt Pending 0 No interrupt 1 Interrupt Register C Register D...
  • Page 77 Chapter 7. Real-Time Clock Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 78: Chapter 8. Serial Controller

    CHAPTER 8. SERIAL CONTROLLER This chapter discusses operation of the two ZT 8905 serial ports. Each channel is compatible with the industry standard 16550 serial port, including support for a 16 byte FIFO for read and write operations. ZT 8905 SPECIFICS The ZT 8905 includes two serial ports that are compatible with the industry standard 16550.

  • Page 79: Interrupt Selection

    Chapter 8. Serial Controller Interrupt Selection The interrupt mapping for the PC standard architecture and the ZT 8905 is shown below. Different interrupt levels for COM1 and COM2 interrupts are selectable through screen 2 of the BIOS SETUP utility. For more on the BIOS SETUP utility, see the section "BIOS SETUP Overview" in Appendix A. Serial Channel PC Interrupt ZT 8905 Interrupt...

  • Page 80: Baud Rate Divisors

    Chapter 8. Serial Controller Baud Rate Divisors The "Divisor Latch LSB" and "Divisor Latch MSB" figures that follow illustrate the 16-bit divisor latch. The "Baud Rate Divisors" table below lists the divisors for popular baud rates. It also includes the percent error based on the difference between the exact divisor for a specified baud rate and the divisor obtainable with a 16-bit integer format.

  • Page 81: Divisor Latch Lsb And Msb

    Chapter 8. Serial Controller Divisor Latch LSB and MSB Register: Divisor Latch LSB Address: 2F8/3F8h DIV=1 Access: Read and Write Divisor Latch LSB Register: Divisor Latch MSB Address: 2F9/3F9h DIV=1 Access: Read and Write Divisor Latch MSB Interrupt Control Register Register: Interrupt Control Address: 2F9/3F9h DIV=0 Access:...

  • Page 82: Interrupt Status Register

    Chapter 8. Serial Controller Interrupt Status Register Register: Interrupt Status Source Address: 2FA, 3FAh Access: Read Interrupt 0 Active 1 Inactive Interrupt Source 000 Modem Status Clear to send Data set ready Ring indicator Data carrier detect 010 Transmit Buffer 100 Receive Buffer 110 Line Status Break...

  • Page 83: Line Status Register

    Chapter 8. Serial Controller Line Status Register Register: Line Status TRB THR BRK FRM PTY OVR RBR Address: 2FD/3FDh Access: Read Receive Buffer 0 Empty 1 Full Overrun Error 0 No error 1 Error Parity Error 0 No error 1 Error Framing Error 0 No error 1 Error...

  • Page 84: Modem Status Register

    Chapter 8. Serial Controller Modem Status Register Register: Modem Status Address: 2FE, 3FEh DCD RIN DSR CTS DDD DDR DCS Access: Read Delta Clear To Send 0 No transition 1 Transition Delta Data Set Ready 0 No transition 1 Transition Ring Indicator Trailing Edge 0 No trailing edge 1 Trailing edge...
  • Page 85 Chapter 8. Serial Controller Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 86: Chapter 9. Ieee-1284 Parallel Port Interface

    CHAPTER 9. IEEE-1284 PARALLEL PORT INTERFACE The ZT 8905 supports an IEEE-1284 compatible printer port interface, available through the Multi-I/O connector (J5). The printer port can be configured in Normal (compatibility), Extended, EPP, or ECP modes through screen 1 of the BIOS SETUP utility (discussed in the section "BIOS SETUP Overview" in Appendix A).

  • Page 87: Address Mapping

    Chapter 9. IEEE-1284 Parallel Port Interface ADDRESS MAPPING The address mapping for the PC standard architecture and the ZT 8905 is shown below. The on- board port may be disabled to allow an STD 32 LPT port to be used. Parallel Port PC Port Address ZT 8905 Port Address...

  • Page 88: Line Printer Status Register

    Chapter 9. IEEE-1284 Parallel Port Interface Line Printer Status Register Register: Line Printer Status BSY ACK SEL ERR Address: 379h Access: Read Printer Interrupt 0 Printer acknowledged 1 Read from status port Printer Error 0 Active 1 Inactive Printer Select 0 Off line 1 On line Paper Empty...

  • Page 89: Additional Information

    Chapter 9. IEEE-1284 Parallel Port Interface ADDITIONAL INFORMATION Refer to the National Semiconductor PC87303 data book (National LIT# 112904-001) for more information on the parallel controller operating modes. An excellent tutorial of IEEE-1284 can be obtained from FarPoint Communications (805) 726-4420. The IEEE-1284 specification can be obtained from the IEEE Standards Office at (800) 678-4333, ask for document number DS02709.

  • Page 90: Chapter 10. Optional Ide Interface

    CHAPTER 10. OPTIONAL IDE INTERFACE The ZT 8905 can be purchased with a local Intelligent Drive Electronics (IDE) Hard Disk Interface attached to the bottom side of the board via a carrier board. This feature is useful for single board applications as well as STAR SYSTEMs where the ZT 8905 needs to have a local (non-shared) hard disk.

  • Page 91: Star System Applications

    Chapter 10. Optional IDE Interface STAR SYSTEM APPLICATIONS Certain STAR SYSTEM applications require that a CPU board have exclusive access to an IDE drive. This can be because the CPU is booting a unique operating system or requires isolated (non- shareable) hard disk capability for performance reasons.

  • Page 92: Chapter 11. System Registers

    CHAPTER 11. SYSTEM REGISTERS There are two system registers used to control and monitor a variety of functions on the ZT 8905. Each register is read/write capable. Normally, only the system BIOS will use the registers, but they are documented for application use as needed. Care must be taken when modifying the contents of these registers as the system BIOS may be relying on the state of the bits under its control.

  • Page 93: System Register 1

    Chapter 11. System Registers System Register 1 Register: System Register 1 STD EXP INT Address: 878h Access: Write/Read Watchdog Timer Strobe 0 Strobe Watchdog (Default) 1 Arm Watchdog STAR SYSTEM Interrupt 0 Inactive 1 Drive Interrupt Exp. Socket SRAM/ROM Select 0 ROM 1 Emulation RAM STD Bus NMI (Read Only)

  • Page 94: Chapter 12. Watchdog Timer

    CHAPTER 12. WATCHDOG TIMER The primary function of the watchdog timer is to monitor ZT 8905 operation and take corrective action if the system fails to function as programmed. The major features of the watchdog timer are listed below. • Single-stage •...
  • Page 95 Chapter 12. Watchdog Timer Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 96: Chapter 13. Pci Mezzanine Local Bus

    CHAPTER 13. PCI MEZZANINE LOCAL BUS The ZT 8905 includes a PCI compatible local bus interface to industry standard PCI mezzanine devices. The bus operates at half of the CPU external clock speed. Ziatech offers PCI peripheral adapters designed specifically for this local bus interface. These adapters give superior performance over STD bus solutions by running with up to four times the data width and up to four times the operating frequency.
  • Page 97 Chapter 13. CompactPCI Mezzanine Local Bus Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 98: Chapter 14. Programmable Led

    CHAPTER 14. PROGRAMMABLE LED The ZT 8905 includes two Light-Emitting Diodes (LEDs). A green LED for the optional IDE disk drive is mounted at the bottom right corner of the board when viewed from the top with the gold fingers to the left.
  • Page 99 Chapter14. Programmable LED Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 100: Appendix A. Board Configuration

    APPENDIX A. BOARD CONFIGURATION The ZT 8905 includes several options that tailor the operation of the board to requirements of specific applications. Most of the options are selected through the BIOS SETUP mechanism. Some options cannot be software controlled and are configured with jumpers or cuttable traces. Jumper options are made by installing and removing shorting receptacles.
  • Page 101 Appendix A. Board Configuration Ziatech Industrial BIOS Setup Utility Copyright (C) 1997, Ziatech Corporation 1.44M Floppy Disk A: ......Floppy Interface ....... STD32 Floppy Disk B: ......IDE Interface ......STD32 COM1 Port ....... ONBOARD 2482 16 63 Fixed Disk 0: ...

  • Page 102: Zt 8905-Specific Setup Options

    Appendix A. Board Configuration ZT 8905-Specific SETUP Options ZT 8905-specific SETUP options, such as interrupt routing and STD 32 memory and I/O addressing, are configurable through screen 2 of the SETUP utility and are discussed below. • Interrupt routing The source for individual interrupt controller inputs is selectable through screen 2 of the SETUP utility.

  • Page 103: Dos Factory Default Jumper Configuration

    Appendix A. Board Configuration The "DOS Factory Default Jumper Configuration" illustration and the "Customer Jumper Configuration" illustration are shown below. The "Customer Jumper Configuration" illustration provides a blank jumper layout allowing you to document your jumper configuration if it differs from the factory default.

  • Page 104: Jumper Cross-Reference Table

    Appendix A. Board Configuration JUMPER CROSS-REFERENCE TABLE The following table divides the jumper options into functional groups. Click on any jumper number for a description of the jumper. Function Jumpers CMOS RAM Erase W1A,W1B Boot From On-Board Flash Device Reserved W1D, W1E Temp Master to ZT 8911 Reserved...

  • Page 105: W1D (Reserved)

    Appendix A. Board Configuration W1D (Reserved) Reserved. This jumper must be left installed. W1E (Reserved) Reserved. This jumper must be left installed. W1F (Temporary Master to ZT 8911) When the ZT 8905 is used in a STAR SYSTEM that has the ZT 8911 as the Permanent Master, jumper W1F must be installed.

  • Page 106: Ct1, Ct2 (Frontplane Dma)

    Appendix A. Board Configuration IDE Hard Disk Interface Floppy Disk Controller Interface ZT8905FA-03 Cuttable Trace Locations CT1, CT2 (Frontplane DMA) CT1 and CT2 assign up to two additional DMA channels for frontplane operation. Function Connects J5 pin 53 to DMA Channel 6 DACK* †...
  • Page 107 Appendix A. Board Configuration Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 108: Appendix B. Specifications

    APPENDIX B. SPECIFICATIONS This appendix describes the electrical, environmental, and mechanical specifications of the ZT 8905. It also includes illustrations of the board dimensions, the P/E connector pinouts, and the cable commonly used with the ZT 8905, as well as tables showing the pin assignments for the ZT 8905's I/O connectors.

  • Page 109: Pentium Processors Maximum Ambient Temperatures

    Appendix B. Specifications Operating Temperature The values in the figure and table referenced below are stress ratings only. Do not operate the ZT 8905 at these maximums. See the "DC Operating Characteristics" section in this appendix for operating conditions. For proper operation of the ZT 8905, the Pentium processor case temperature must remain below 70°...

  • Page 110: Dc Operating Characteristics

    Appendix B. Specifications DC Operating Characteristics • Supply VoltageVcc: 4.75 to 5.25 V • Supply Voltage, AUX +: 11.4 to 12.6 V (for 4 Mbyte Flash programming) • Supply Voltage, AUX -: Not used • Supply Current, Icc: Pentium-100: 2.1 A typ., 2.9 max. (Numbers assume 8 Mbytes of DRAM Pentium-133: 2.3 A typ., 3.1 max.

  • Page 111: Std Bus Loading Characteristics

    Appendix B. Specifications STD Bus Loading Characteristics The unit load is a convenient method for specifying the input and output drive capability of STD bus cards. With this method, one unit load is equal to one LSTTL load as follows: •...

  • Page 112: Std Bus Loading, E Connector

    Appendix B. Specifications STD Bus Loading, E Connector PIN (CIRCUIT SIDE) PIN (COMPONENT SIDE) OUTPUT DRIVE OUTPUT DRIVE INPUT LOAD INPUT LOAD MNEMONIC MNEMONIC LOCK* XA23 XA19 XA22 XA18 XA21 XA17 XA20 XA16 RSVD NOWS* +5 VDC +5 VDC DREQx* DAKx* MASTER16* AENx*...

  • Page 113: Mechanical

    2.54 cm (1 inch) --From bottom surface: 0.12 cm (0.047 inches) The ZT 8906, with its CompactPCI enclosure, occupies a total of six STD 32 card slots, allowing three CompactPCI peripherals to be used inside an STD 32 card cage. 6.500 0.025...

  • Page 114: Connectors

    Appendix B. Specifications Connectors As shown in the "Connector Locations" illustration, the ZT 8905 includes several connectors to interface to the STD bus and application-specific devices. The topics that follow provide descriptions of the individual connectors. Connector assignments are listed below. Please note the revision of the ZT 8905 that you are using.

  • Page 115: P/E (Std-80/Std 32 Bus)

    Appendix B. Specifications P/E (STD-80/STD 32 Bus) The E connector interfaces the ZT 8905 to the STD 32 bus. This connector combines the STD-80 interface (on the P pins) with the additional signals defined for STD 32 (on the E pins) to make a 136-pin (dual 68-pin) card-edge connector with fingers on 0.0625 inch contact spacing.

  • Page 116: J1 (L2 Cache Module)

    Appendix B. Specifications J1 (L2 Cache Module) J1 is a 36-pin location for an optional L2 cache module. Contact Ziatech for availability. J2 (Fan Connector) J2 is a 3-pin vertical male header with 0.1 inch contact spacing for supplying power to the fan/heatsink.

  • Page 117: J3 (Pci Local Bus Interface)

    Appendix B. Specifications J3 (PCI Local Bus Interface) J3 is a 175-pin 2 mm x 2 mm female receptacle providing the PCI local bus interface to optional mezzanine adapters designed for this application. J3 provides a complete 32-bit PCI interface. This connector is CompactPCI compatible.

  • Page 118: J4 (Vga Transition Connector)

    Appendix B. Specifications J4 (VGA Transition Connector) J4 provides an interface for optional PCI VGA Interface boards to pass down the video signals to the ZT 8905 for routing through the J5 multi-I/O connector interface. This mechanism allows all cabling to be done through J5, including the VGA interface.

  • Page 119: J5 Multi-I/O Connector Pinout

    Appendix B. Specifications J5 Multi-I/O Connector Pinout Description Type Signal Pin # Pin # Signal Type Description ------ Ground DRQ6* DMA Request 6 Configurable FP1* DRQ1* DMA Request 1 Ground ------ DAK6* DMA Acknowledge 6 Configurable FP3* DAK1* DMA Acknowledge 1 ------ Ground DRQ7*...

  • Page 120: J6 (Floppy Disk Controller Interface)

    Appendix B. Specifications J6 (Floppy Disk Controller Interface) J6 is a surface mount connector location for an optional floppy disk controller interface. Contact Ziatech for details. This interface is provided primarily for single board computer operation (without an STD 32 backplane). STD 32 users should use the ZT 8954 Floppy Disk Controller Interface for floppy support.

  • Page 121: Cable

    Appendix B. Specifications Cable The following cable is available from Ziatech Corporation. A drawing is included here as reference for those who wish to make their own cable: ZT 90205 Multi-I/O cable supports VGA, keyboard, COM1, COM2, LPT1, DMA, and Interrupts through J5.

  • Page 122: Appendix C. Customer Support

    APPENDIX C. CUSTOMER SUPPORT This appendix offers technical assistance information for this product, and also the necessary information should you need to return a Ziatech product. TECHNICAL/SALES ASSISTANCE If you have a technical question, please call Ziatech's Customer Support Service at one of the numbers below, or e-mail our technical support team at tech_support@ziatech.com.

  • Page 123: Reliability

    • Accessing I/O in the address ranges of 500-7FFh and 900-FFFh now go off-board to the STD backplane/system ZT 8906 Revision A - 3/22/96 Revision A is the first production release of the ZT 8906 board. Revision A.1 - 5/3/96 There are no functional changes between Revision A and Revision A.1. Revision A.3 - 6/17/97 There are no functional changes between Revision A.2 and Revision A.3.

  • Page 124: Returning For Service

    These topics are covered in the following sections. Five-Year Limited Warranty Products manufactured by Ziatech Corporation are covered from the date of purchase by a five-year warranty against defects in materials, workmanship, and published specifications applicable to the date of manufacture. During the warranty period, Ziatech will repair or replace, solely at its option, defective units provided they are returned at customer expense to an authorized Ziatech repair facility.

  • Page 125: Special Extended Warranty Option

    Ziatech products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Ziatech Corporation. As used herein: 1. Life support devices or systems are devices or systems which support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

  • Page 126: Appendix D. Pci Configuration Space Map

    APPENDIX D. PCI CONFIGURATION SPACE MAP All PCI compliant devices contain a PCI configuration header. The generic layout of the header is shown in the "PCI Configuration Header" diagram on the following page. Additionally, a device may contain unique configuration registers (at location > 40h). For the ZT 8905, these are shown in the "ZT 8905 On-Board Device PCI Bus Mapping"...
  • Page 127 Appendix D. PCI Configuration Space Map Device ID Vendor ID Status Command Class Code Revision ID Header Cache Line Latency BIST Type Size Timer Base Address Registers Cardbus CIS Pointer Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Reserved Interrupt Interrupt...
  • Page 128 INDEX - 1 - 146818 real-time clock Real-Time Clock Real-Time Clock Overview...................... 57 16550-compatible serial ports Serial Controller Serial Controller Overview....................... 61 - 8 - 8237 direct memory access controller DMA Controller DMA Controller Overview ......................47 8254 counter/timer Counter/Timers Counter/Timers Overview......................
  • Page 129 Index address mapping IEEE-1284 Parallel Port Interface Address Mapping ........................70 Serial Controller Address Mapping ........................61 address multiplexing, STD-80 bus spec STD 32 Bus Interface STD-80 Peripheral Support, Address Multiplexing ..............21 address register (DMA controller) DMA Controller DMA Controller Registers, Address Register................50 addressing (see I/O addr.
  • Page 130 Index battery backup Getting Started System Configuration Overview ....................17 battery backup characteristics Specifications Electrical and Environmental, Battery Backup Characteristics..........93 baud rate divisors Serial Controller Baud Rate Divisors Table......................63 Serial Controller Registers, Baud Rate Divisors..............63 Serial Controller Registers, Divisor Latch LSB/MSB ............... 64 BIOS SETUP Board Configuration BIOS SETUP Overview ......................
  • Page 131 Index boot sequence, system configuration Getting Started Operating System Installation ....................19 System Configuration Overview....................17 bus interface (see STD 32 bus interface) Introduction Functional Blocks, STD 32 Bus Interface .................. 5 bus loading characteristics and tables Specifications Electrical and Environmental, STD Bus Loading Charac., Intro..........94 Electrical and Environmental, Table--STD Bus Loading, E Connector........
  • Page 132 Index clear master register (DMA controller) DMA Controller DMA Controller Registers, Clear Master Register..............54 clock, real-time Introduction Functional Blocks, Real-Time Clock ..................8 Real-Time Clock Real-Time Clock Additional Information.................. 59 Real-Time Clock Overview...................... 57 Real-Time Clock Programmable Registers................57 COM ports Serial Controller ZT 8905 Specifics........................
  • Page 133 Index configuration Getting Started Operating System Installation ....................19 System Configuration Overview....................17 ZT 8905 Setup ......................... 16 configuration header and space map, PCI PCI Configuration Space Map Overview ..........................109 configuration options Board Configuration BIOS SETUP Overview ......................83 Overview ..........................
  • Page 134 Index count register (DMA controller) DMA Controller DMA Controller Registers, Count Register................50 count register illustration Counter/Timers Count Registers And Count Latch................... 42 count registers and count latch Counter/Timers Count Registers And Count Latch................... 42 counter/timer architecture illustration Counter/Timers Counter/Timer Architecture Illustration..................41 counter/timer operating modes table Counter/Timers Counter/Timer Operating Modes Table...................
  • Page 135 Index Cuttable Trace Locations (illus.) Board Configuration Cuttable Trace Options, Illus.--CT Locations................89 cuttable trace options and locations Board Configuration Cuttable Trace Options And Locations ..................88 Cuttable Trace Options, Illus.--CT Locations................89 - D - damage during shipping Customer Support Returning for Service ......................
  • Page 136 Index Board Configuration Cuttable Trace Descriptions, CT1/CT2 (Frontplane DMA)............89 Introduction Functional Blocks, DMA ......................7 Specifications Mechanical, Connectors, J5 (Multi-I/O Connector) ............... 101 STD 32 Bus Interface STD-80 Peripheral Support, DMA Slave Support..............22 DMA architecture illustration DMA Controller DMA Architecture Illustration ....................
  • Page 137 Index DRAM Getting Started Memory Configuration......................12 Typical DRAM Configurations Table..................12 Introduction Functional Blocks, Memory and I/O Addressing ................ 6 DS1236 system monitor Watchdog Timer Watchdog Timer Operation ..................... 77 - E - E/P connectors (STD 32/STD-80 bus interface) Specifications Mechanical, Connectors, P/E (STD-80/STD 32 Interface) ............
  • Page 138 Index expansion socket Getting Started Memory Configuration ......................12 System Registers System Registers, System Register 1..................76 extended architecture (EA) STD 32 Bus Interface STD 32 Bus Compatibility, Extended Architecture ..............23 extended warranty policy Customer Support Warranty, Intro........................107 external LED Specifications Mechanical, Connectors, J5 (Multi-I/O Connector) ...............
  • Page 139 Index Introduction Functional Blocks, Memory and I/O Addressing ................ 6 System Registers System Registers, System Register 0 ..................75 floppy disk controller interface (J6 connector) Specifications Mechanical, Connectors, J6 (Floppy Disk Controller Interface)..........103 frontplane DMA Board Configuration Cuttable Trace Descriptions, CT1/CT2 (Frontplane DMA) ............89 DMA Controller DMA Controller, ZT 8905 Specifics..................
  • Page 140 Index getting started Getting Started Connector Configuration ......................15 Overview..........................11 I/O Configuration ........................13 Jumper Descriptions........................ 16 Memory Configuration ......................12 System Requirements ......................11 Unpacking ..........................11 What's In The Box? ......................... 11 - H - handshaking Serial Controller Handshake Signals .........................
  • Page 141 Index I/O addressing Getting Started I/O Configuration........................13 Introduction Functional Blocks, Memory and I/O Addressing ................ 6 Programmable Registers, Counter/Timer Register Addressing Table ........... 42 Serial Controller Serial Controller Programmable Registers ................62 Address Mapping ........................61 STD 32 Bus Interface STD 32 Bus Compatibility, Extended Architecture..............
  • Page 142 Index installing an operating system Getting Started Operating System Installation....................19 Integrated Drive Electronics (see IDE) Specifications Mechanical, Connectors, J7 (IDE Hard Disk Connector) ............103 integrated fan/heatsink Getting Started System Requirements ......................11 Specifications Mechanical, Card Dimensions And Weight................96 intelligent I/O architecture STD 32 Bus Interface Multiple Master and Intelligent I/O, Intelligent I/O..............
  • Page 143 Index interrupt initialization programming illustration Interrupt Controller Interrupt Controller Initialization Registers (ICW1-ICW4) ............34 interrupt status register (serial controller) Serial Controller Serial Controller Registers, Interrupt Status Register .............. 65 interrupts Interrupt Controller Interrupt Controller Extended Mode Register ................40 Interrupt Controller Overview ....................31 Introduction Functional Blocks, Interrupts......................
  • Page 144 Index - J - J1 connector (optional L2 cache module) Specifications Mechanical, Connectors, J1 (L2 Cache Module) ..............99 J2 connector (fan connector) Specifications Mechanical, Connectors, J2 (Fan Connector)................. 99 J3 connector (CompactPCI local bus) Specifications Mechanical, Connectors, J3 (CompactPCI Local Bus Interface) .......... 100 J4 connector (VGA transition connector) Specifications Mechanical, Connectors, J4 (VGA Transition Connector) ............
  • Page 145 Index Jumper Cross-Reference Table Board Configuration Jumper Cross-Reference Table....................87 jumper descriptions (see also W1A, W1B, etc.) Board Configuration Jumper Cross-Reference Table....................87 Jumper Descriptions, Intro....................... 87 Jumper Descriptions, W1A, W1B (CMOS RAM Erase) ............87 Jumper Descriptions, W1C (Boot From Onboard Flash)............87 Jumper Descriptions, W1D (Reserved) ...................
  • Page 146 Index level-triggered interrupts STD 32 Bus Interface STD Bus Interrupts, Maskable Interrupts ................24 life support policy Customer Support Warranty, Intro........................107 line control register (serial controller) Serial Controller Serial Controller Registers, Line Control Register..............65 line printer control register (IEEE 1284 parallel port interface) IEEE-1284 Parallel Port Interface Parallel Port Interface Line Printer Control Register ...............
  • Page 147 Index - M - maskable interrupts STD 32 Bus Interface STD Bus Interrupts, Intro......................24 STD Bus Interrupts, Maskable Interrupts................. 24 STD-80 Peripheral Support, Interrupts ..................22 maximum ratings Specifications Electrical and Environmental, Absolute Maximum Ratings ............. 91 mechanical dimensions Specifications Mechanical, Card Dimensions And Weight ................
  • Page 148 Index modem status register (serial controller) Serial Controller Serial Controller Registers, Modem Status Register............... 67 multi-I/O cable ZT 90205 (illus.) Specifications Cable, Illus--ZT 90205 Multi-I/O Cable.................. 104 multi-I/O connector (J5) Board Configuration Cuttable Trace Descriptions, CT1/CT2 (Frontplane DMA)............89 DMA Controller DMA Controller, ZT 8905 Specifics ..................
  • Page 149 Index - N - Non-Maskable Interrupt Structure (illus.) STD 32 Bus Interface STD Bus Interrupts, Illus.--Non-Maskable Int Structure............26 non-maskable interrupts STD 32 Bus Interface STD Bus Interrupts, Intro......................24 STD Bus Interrupts, Non-Maskable Interrupts................. 26 System Registers System Registers, System Register 1 ..................76 Watchdog Timer Watchdog Timer Operation .....................
  • Page 150 Index optional L2 cache module (J1 connector) Specifications Mechanical, Connectors, J1 (L2 Cache Module) ..............99 - P - P/E Connector Pinout (illus.) Specifications Mechanical, Connectors, Illus.--P/E Connector Pinout ............98 P/E connectors (STD-80/STD 32 bus interface) Specifications Mechanical, Connectors, P/E (STD-80/STD 32 Interface)............98 parallel I/O IEEE-1284 Parallel Port Interface IEEE 1284 Parallel Port Interface Overview................
  • Page 151 Index Pentium (P54C) family of microprocessors Introduction Functional Blocks, Pentium Processors ..................5 Pentium Processor Comparison Table ..................5 Product Definition, Intro......................1 peripheral devices Introduction Product Definition, Stand-Alone Operation ................1 STD 32 Bus Interface STD-80 Peripheral Support, Intro.................... 21 permanent master STD 32 Bus Interface Multiple Master System Requirements ..................
  • Page 152 Index - R - real-time clock Introduction Functional Blocks, Real-Time Clock ..................8 Real-Time Clock Real-Time Clock Additional Information.................. 59 Real-Time Clock Overview...................... 57 Real-Time Clock Programmable Registers................57 Real-Time Clock Register Addressing (table) Real-Time Clock Real-Time Clock Register Addressing Table ................57 receive buffer (serial controller) Serial Controller Serial Controller Register Addressing Table ................
  • Page 153 Index registers (continued) DMA Controller DMA Controller Registers, Clear Master Register ..............54 DMA Controller Registers, Command Register ............... 51 DMA Controller Registers, Count Register ................50 DMA Controller Registers, DMA Extended Mode Register............53 DMA Controller Registers, DMA Extended Page Register ............55 DMA Controller Registers, DMA Page Register ..............
  • Page 154 Index reserved jumpers (W1E, W2, W3) Board Configuration Jumper Descriptions, W1E (Reserved)................... 88 Jumper Descriptions, W2 and W3 (Reserved) ............... 88 reset STD 32 Bus Interface Multiple Master and Intelligent I/O, Reset................30 Reset ............................26 Watchdog Timer Watchdog Timer Operation ..................... 77 resistor packs for perm.
  • Page 155 Index Serial Controller Register Addressing (table) Serial Controller Serial Controller Register Addressing Table................62 serial I/O Introduction Functional Blocks, Serial I/O...................... 6 Serial Controller ZT 8905 Specifics ........................61 Serial Controller Additional Information ................... 67 Serial Controller Overview ....................... 61 Serial Controller Programmable Registers ................
  • Page 156 Index socket T6C location STD 32 Bus Interface Socket T6C Location Drawing....................29 software development Introduction Development Considerations ....................3 speaker interface Introduction Functional Blocks, Speaker Interface..................9 Specifications Mechanical, Connectors, J5 (Multi-I/O Connector) ............... 101 specifications Specifications Electrical and Environmental, Intro..................91 Mechanical, Intro.
  • Page 157 Index status registers Counter/Timers Counter/Timer Status Register ....................43 DMA Controller DMA Controller Registers, Status Register................51 Interrupt Controller Interrupt Controller Status Registers (IRR, ISR, IPR) .............. 38 STD 32 background STD 32 Bus Interface STD 32 Background......................... 21 STD 32 bus interface Introduction Functional Blocks, STD 32 Bus Interface ..................
  • Page 158 Index STD Bus Vectored Interrupt Structure (illus.) STD 32 Bus Interface STD Bus Interrupts, Illus.--Vectored Int Structure ..............25 STD-80 peripheral support STD 32 Bus Interface STD-80 Peripheral Support, Address Multiplexing..............21 STD-80 Peripheral Support, DMA Slave Support..............22 STD-80 Peripheral Support, I/O Expansion ................22 STD-80 Peripheral Support, Interrupts..................
  • Page 159 Index temporary master Board Configuration Jumper Descriptions, W1F (Temp Master to ZT 8911) ............88 STD 32 Bus Interface Multiple Master System Requirements ..................28 Multiple Master and Intelligent I/O, Multiple Master ..............27 Multiple Master and Intelligent I/O, Reset ................30 Watchdog Timer Watchdog Timer Operation .....................
  • Page 160 Index - W - W1A, W1B (CMOS RAM Erase) Board Configuration Jumper Descriptions, W1A, W1B (CMOS RAM Erase) ............87 W1C (boot from onboard Flash device) Board Configuration Jumper Descriptions, W1C (Boot From Onboard Flash) ............87 W1D (reserved) Board Configuration Jumper Descriptions, W1D (Reserved) ..................
  • Page 161 Product Definition, Intro......................1 Specifications Mechanical, Card Dimensions And Weight ................96 ZT 8905 setup Board Configuration ZT 8905-Specific SETUP Options ................... 85 ZT 8906 Introduction Product Definition, Intro......................1 Specifications Mechanical, Card Dimensions And Weight ................96 xxxiv...
  • Page 162 Index ZT 8911 Scalable Processor Board Board Configuration Jumper Descriptions, W1F (Temp Master to ZT 8911) ............88 STD 32 Bus Interface Multiple Master System Requirements..................28 ZT 8954 Floppy Disk Controller Interface Specifications Mechanical, Connectors, J6 (Floppy Disk Controller Interface) ..........103 ZT 89CT39 arbiter card STD 32 Bus Interface Multiple Master System Requirements..................
  • Page 163 Index xxxvi Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 164 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 165 1050 Southwood Drive • San Luis Obispo, CA 93401 USA • Tel (805) 541-0488 • FAX (805) 541-5088 Central Regional Office Eastern Regional Office European Office 7700 Chevy Chase Drive, Suite 110-A 319 North Pottstown Pike, Suite 107 P.O. Box 110 Austin, TX 78752 USA Exton, Pennsylvania 19341 USA AC SON...
  • Page 166 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...

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