Port Allocations; Cpu - Icom IC-2720H Service Manual

4-5 PORT ALLOCATIONS

4-5-1 CPU (MAIN UNIT; IC2013)
Pin Port
number name
Outputs microphone mute signal for
10 UMMUTE right side display.
Low: While microphone is muting.
11 CK_SHIFT1 Output clock shift signal.
Outputs transmit mute control signal.
16 TX_MUTE
High:While transmit is muting.
Input port for microphone's PTT detect-
17 MIC_PTT
ing signal.
18 SUB_SEL Outputs sub band select signal.
Outputs RF transmit power supply cir-
cuit control signal for left side display.
20 UTX_CTRL
High:While transmitting 400–479
Outputs RF transmit power supply cir-
cuit control signal for right side display.
21 VTX_CTRL
High:While transmitting 136–174
22 DTCS_SEL
Outputs DTCS filter select signal.
I/O port the data signal from/to the
24 ES_DATA
EEPROM (IC2000, pin 5).
Outputs clock signal to the EEPROM
25 ES_CK
(IC2000, pin 6).
Input port for PTT detect signal in pack-
26 P_PTT
et mode.
Outputs modulation mute signal on
27 P_MOD_MUTE
packet mode
Low: While packet mod. is muting.
28 98_DATA Input port for data signal from HM-98.
Input port for up/down signal from the
29 MIC_U/D
microphone.
Outputs the microphone mute signal to
30 CM_MUTE the CONTROL unit.
Low: While the microphone is muting.
Input port for the connecting micro-
31 MIC_SEL
phone detect signal for HM-98.
Low: While HM-98 is connecting.
Input port for the RSSI signal from the
FM IF IC (IC1004, pin 12) to detect
32 R_RSSI
receiving signal strength for right side
display.
Input port for the RSSI signal from the
FM IF IC
33 L_RSSI
receiving signal strength for left side
display.
Input port for chassis temperature
34 TEMP
detecting signal.
Input port for the reverse power detect-
35 REV_DET
ing signal.
Input port for the squelch level for right
38 R_SQL
side display.
Input port for the DTCS or CTCSS sig-
39 R_DTCS_IN
nal for right side display.
Input port for the squelch level for the
40 L_SQL
left side display.
Input port for the DTCS or CTCSS sig-
41 L_DTCS_IN
nal for left side display.
44 DTMF
Outputs DTMF, E-tone, beep signals.
45 DTCS
Outputs DTCS and CTCSS signals
47 P_SQL Outputs the packet squelch signal.
Description
MHz.
MHz.
(IC1001, pin 12)to detect
Pin Port
number name
48 FAN_CTRL
49 CLONE_OUT
50 CLONE_IN
51 D/A_DATA
52 D/A_CK
53 D/A_STB
54 MM_MUTE
55 L_AF_MUTE
56 R_AF_MUTE
57 L_DET_MUTE
58 R_DET_MUTE
60 AF_VOL_CK
61 AF_VOL_DATA
62 L_R5CTRL
63 R_UVCO_SEL
64 L_UNLOCK
65 1200/9600SEL
66 L_RX400
67 L_RX300
68 L_AM
69 R_AM
72 R_RX220
73 L_RX140
74 R_RX800
4 - 10
Description
Outputs cooling fan control signal.
Outputs the cloing data signal.
Input port for the cloing data signal.
Outputs serial data to the D/A convert-
er IC (IC1, pins 15–17).
Outputs microphone mute control sig-
nal for MAIN unit.
Low: While the microphone is muting.
Outputs AF mute control signal for left
side display.
High:While AF audio is muting.
Outputs AF mute control signal for right
side display.
High:While AF audio is muting.
Outputs detector mute signal for left
side display.
Outputs detector mute signal for right
side display.
Outputs the volume serial signal.
Outputs the RX RF power supply con-
trol signal for left side display.
Outputs the VCO select signal for right
side display.
High:While receiving 320–999.9 MHz
on right side display.
Input port for the PLL unlock signal for
left side display (VCO unit; IC1, pin 7).
Low: The PLL Lock voltage is unlock
for left side display.
Outputs 1200or 9600 bps packet baud
rate select signal.
Low: 9600 bps baud rate is selected.
Outputs the 400 MHz receiver circuit
select signal for left side display.
High:While receiving 310–550 MHz
on left side display.
Outputs the 300 MHz receiver circuit
select signal for left side display.
High:While receiving 205–309.995
MHz on left side display.
Outputs receive mode select signal for
left side display.
Low: AM mode is selected.
Outputs receive mode select signal for
right side display.
Low: AM mode is selected.
Outputs the 220 MHz receiver circuit
select signal for left side display.
Low: While receiving 174–254.995
MHz on left side display.
Outputs the 144 MHz receiver circuit
select signal for left side display.
Low: While receiving 118–173.995
MHz on left side display.
Outputs the 800 MHz receiver circuit
select signal for right side display.
Low: While receiving 810–999.990
MHz on right side display.