Sony DVP-CX777ES Service Manual page 122

DVP-CX777ES
Pin No. Pin Name
VDD
61
VSS
62
DLDRI
63
64 CSWI
SLSRI
65
FLFRI
66
TEST3
67
CLK512
68
VSS
69
XRST
70
VDD
71
SCLK
72
XCS
73
SI
74
SO
75
DEXRI
76
DMLI
77
DMRI
78
79 VSS
80 PHAI
81 BCKAI
82 DQM
83 DLI
DRI
84
DCI
85
DLFEI
86
87 DLSI
DRSI
88
VSS
89
90 to 95 D15 to D10
96 VDD
97, 98 D9, D8
GND
99
100 D0
122
I/O
—
Power supply terminal (+3.3V)
—
Ground terminal
I
Audio data input from the audio DSP
I Audio data (for center and woofer) input from the audio DSP
I
Audio data (for rear) input from the audio DSP
I
Audio data (for front) input from the audio DSP
I
Input terminal for the test
I
Master clock (27 MHz) input from the clock generator
—
Ground terminal
I
Reset signal input from the system controller "L": reset
—
Power supply terminal (+3.3V)
I
Serial clock signal input from the system controller
I
Chip select signal input from the mechanism controller
I
Serial data input from the system controller
O
Serial data output to the system controller
I
Not used
I
DSD data input for L-ch down mix to the DSD decoder
I
DSD data input for R-ch down mix to the DSD decoder
— Ground terminal
I
Clock signal input from DSD decoder
I
Bit clock signal input for DSD data output from DSD decoder
O
Not used
I DSD data (for front L-ch) input from DSD decoder
O
DSD data (for front R-ch) input from DSD decoder
O
DSD data (for center) input from DSD decoder
O
DSD data (for woofer) input from DSD decoder
O DSD data (for rear L-ch) input from DSD decoder
O
DSD data (for rear R-ch) input from DSD decoder
—
Ground terminal
I/O
Two-way data bus with the SD-RAM
— Power supply terminal (+3.3V)
I/O
Two-way data bus with the SD-RAM
—
Ground terminal
I/O
Two-way data bus with the SD-RAM
Description