Chipset; Overview; Amd I/O Bridges; Hypertransport 3 (Ht3) - Dell PowerEdge R715 Technical Manual

Dell

7 Chipset

7.1 Overview

The PowerEdge R715 planar incorporates a dual I/O Bridge (IOB) configuration, using the AMD SR5650
and SR5670 I/O bridges with the SP5100 Southbridge. SR5650 and SR5670 are designed to support
AMD's G34 processor family, HyperTransport 3 Interface (@ 2.6 GHz), DDR3 memory technology, and
PCI Express Generation 2. The chipset consists of the SR5650, SR5670, and SP5100.

7.2 AMD I/O Bridges

The PowerEdge R715 I/O Board uses the AMD SR5650 and SR5670 IOBs to provide links between the
G34 processor(s) and I/O components. The main components of the I/O controllers are configured to
use two x16 HyperTransport 3 links (to CPU1 and CPU2), up to 46 lanes of PCI Express Gen 2, an x4
PCIe Gen 1 Southbridge Interface (SB Link), and an integrated IOAPIC. AMD SR5650 is IOB1 (primary)
and AMD SR5750 is IOB2. CPU1 has direct HT3 link to IOB1 and CPU2 has direct HT3 link to IOB2. IOB1
has the Southbridge interface.

7.3 HyperTransport 3 (HT3)

The HyperTransport 3 consists of serial point-to-point interconnects for the processors and the I/O
bridges. The PowerEdge R715 has a total of four HyperTransport (HT3) x16 links per processor, which
allow each processor to be interconnected with each other with options for I/O Bridges. Each I/O
Bridge has a single x16 HT3 link. A full Link consists of 16 lanes (full-width + ganged) in each
direction with a link speed of 6.4 GT/s. The HT3 clocking for CPU HT3 and IOB HT3 are 3.2 GHz and
2.6 GHz, respectively. Therefore, the IOB HT3 link is capable of 5.2 GT/s. For routing, the HT3 links
are grouped by x8 Command Address (CAD), x1 Control (CTL), and x1 Clock (CLK) for each RX and TX
directions. Half links consist of 8 lanes in each direction with a link speed of 6.4 GT/s, and are
considered unganged. There is throughput benefit with ganged links.

7.4 PCI Express Expansion

PCI Express is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles the
signaling bit rate of Generation 1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports is backward-
compatible with Gen1 transfer rates.
The combined IOBs yield 46 PCI Express lanes. IOB1 has a x8 port that interfaces with Riser 1 PLX
PCIe Gen 2 Bridge. The lanes are partitioned as follows:

1 PCI Express Gen2 x8 port from IOB1 to Riser1 PLX
o 1 PCI Express Gen2 x8 port (slot 1)
o 1 PCI Express Gen2 x4 port (slot 2)
o 1 PCI Express Gen2 x4 port dedicated to storage adapter (storage)

2 PCI Express Gen2 ports for LOM (x4 for LOM1 and x2 for LOM2)

1 PCI Express Gen2 x8 port from IOB1 (slot 4)

1 PCI Express Gen2 x8 port from IOB2 (slot 3)

2 PCI Express Gen2 x8 ports from IOB2 Riser2 (slots 5 and 6)

7.5 Southbridge Link Interface

The Southbridge (SB) Link connects the SR5650 IOB with the AMD Southbridge SP5100. The SB Link (A-
Link Express) is equivalent to an x4 PCIe Gen 1 link with a transfer rate of 1 GB/s in each direction.
PowerEdge R715 Technical Guide 31