Chipset Overview - Supero H8DM3-2 User Manual

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Chipset Overview

The H8DM3-2/H8DMi-2 serverboard is based on the nVidia MCP55 Pro/AMD-8132
chipset. The nVidia MCP55 Pro functions as Media and Communications Proces-
sor (MCP). Controllers for the system memory are integrated directly into the AMD
Opteron processors.
MCP55 Pro Media and Communications Processor
The MCP55 Pro is a single-chip, high-performance HyperTransport peripheral con-
troller. It includes a 28-lane PCI Express interface, an AMD Opteron 16-bit Hyper
Transport interface link, a six-port Serial ATA interface, a dual-port Gb Ethernet
interface, a dual ATA133 bus master interface and a USB 2.0 interface. This hub
connects directly to CPU#1 and through that to CPU#2.
8132 HyperTransport PCI-X Tunnel
This hub includes AMD-specifi c technology that provides two PCI-X bridges with
each bridge supporting a 64-bit data bus as well as separate PCI-X operational
modes and independent transfer rates. Each bridge supports up to fi ve PCI mas-
ters that include clock, request and grant signals. The 8132 tunnel connects to the
processors and through them to system memory. It also interfaces directly with the
Serial ATA and Ethernet controllers.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more effi cient use of memory in
multi-processor systems. The end result is a signifi cant increase in bandwidth
within the chipset.
Chapter 1: Introduction
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