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M
X
4
6
M
X
4
6
P
P
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B
S
S
R
R
A
A
M
M
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(
P
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p
p
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For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address decoding time
and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is 3-1-1-1, total 6 clocks, which is
faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and Socket 370 CPU do not need
PBSRAM.
P
C
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1
0
0
D
I
M
M
P
C
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1
0
0
D
I
M
M
SDRAM
DIMM that supports 100MHz CPU
P
C
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1
3
3
D
I
M
M
P
C
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1
3
3
D
I
M
M
SDRAM
DIMM that supports 133MHz CPU
P
C
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1
6
0
0
o
r
P
C
-
2
1
0
P
C
-
1
6
0
0
o
r
P
C
-
2
1
0
Based on FSB frequency, the DDR DRAM has 200MHz and 266MHz two type of working frequency. Because of DDR DRAM data bus is
64-bit, it provides data transfer bandwidth up to 200x64/8=1600MB/s, and 266x64/8=2100MB/s. Hence, the PC-1600 DDR DRAM is
working with 100MHz and PC-2100 DDR DRAM is working with 133MHz FSB frequency.
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P
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Bus for the internal connection of peripheral devices, high-speed data channel between the computer and expansion card.
d
d
B
B
u
u
r
r
s
s
t
t
S
S
R
R
A
A
M
M
)
)
FSB
bus clock.
FSB
bus clock.
0
D
D
R
D
R
A
M
0
D
D
R
D
R
A
M
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