Sas Expander; Figure 5: Vitesse* Vsc410 Block Diagram - Intel SSR212MC2 - Storage Server Hard Drive Array Specification

Feature Summary Intel® Storage Server SSR212MC2

Figure 5: Vitesse* VSC410 Block Diagram

A PLL is used to generate the internal core clock of 40.0MHz from an external 4.0MHz clock
source or crystal. Additional external component are limited to a single SPI Flash memory
device and Two-Wire Serial peripherals dedicated to system management functions.
1.6

SAS Expander

The PMC-Sierra* PM8388 SXP 24×3G device is a 24-port SAS Expander device featuring low
latency connection arbitration, table routing, arbitrary SAS wide ports, SAS SSP/STP targets,
integrated RISC processor for SAS SMP functions and SES support.
All target ports support spin-up control and the STP bridge function allowing either a SAS or
SATA target device to be attached. The PM8388 device supports table routing of up to 1024
entries, direct routing and subtractive routing methods. The non-blocking crossbar in the data
path allows any-port to any-port connections including arbitrary wide port configurations.
The PM8388 device provides in-band access to the Expander internal state information via
proprietary commands within the integrated SMP function. The PM8388 device provides three
multi-master TWI interfaces with independent reset for device configuration or control of
peripheral devices. One UART interface is provided for debugging support.
10 Revision 1.2