Usb; Sata Support - Intel D425KT Technical Product Specification

1.5.2

USB

The board provides up to eight USB 2.0 ports, supports UHCI and EHCI, and uses
UHCI- and EHCI-compatible drivers. The port arrangement is as follows:
Eight USB 2.0 ports (D425KT only):
•
 Four back panel ports
 Four ports are implemented with two dual port internal headers for front panel
cabling
Seven USB 2.0 ports (D425KTW only):
•
 Four back panel ports
 Two ports are implemented with a dual port internal header for front panel
cabling
 One port is implemented with an internal header (brown-colored) that supports
®
an Intel
NOTE
Computer systems that have an unshielded cable attached to a USB port may not meet
FCC Class B requirements, even if no device is attached to the cable. Use shielded
cable that meets the requirements for full-speed devices.
For information about
The location of the USB connectors on the back panel
The location of the front panel USB headers
1.5.3

SATA Support

The board provides two SATA interface connectors that support one device per
connector.
The board's SATA controller offers independent SATA ports with a theoretical
maximum transfer rate of 3.0 Gbits/s on each port. One device can be installed on
each port for a maximum of two SATA devices. A point-to-point interface is used for
host to device connections, unlike PATA which supports a master/slave configuration
and two devices on each channel.
For compatibility, the underlying SATA functionality is transparent to the operating
system. The SATA controller supports IDE and AHCI configuration and can operate in
both legacy and native modes. In legacy mode, standard ATA I/O and IRQ resources
are assigned (IRQ 14 and 15). In native mode, standard PCI Conventional bus
resource steering is used. Native mode is the preferred mode for configurations using
the Windows* XP and Windows Vista* operating systems.
For information about
Obtaining AHCI driver
The location of the SATA connectors
Z-U130 USB Solid-State Drive or compatible device
Product Description
Refer to
Figure 8, page 39
Figure 10, page 41
Refer to
Section 1.2, page 16
Figure 10, page 41
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