Timing Diagrams - DLP Design USB-Parallel FIFO Module DLP-USB245R User Manual

2.0 TIMING DIAGRAMS

RXF#
RD#
D[7 ..0]
D
Description Min Max Unit
T I M E D E S C
T I M E D E S C
T1 RD# Active Pulse Width
T2 RD# to RD# Pre-Charge Time
T3 RD# Active to Valid Data*
T4 Valid Data Hold Time from RD# Inactive*
T5 RD# Inactive to RXF#
T6 RXF# Inactive After RD Cycle
*Load = 30pF
TXE#
WR
D[7 ..0]
T T I I M M E E D D E E S S C C
T7 WR Active Pulse Width
T8 WR to WR Pre-Charge Time
T9 Valid Data Setup to WR Falling Edge*
T10 Valid Data Hold Time from WR Inactive*
T11 WR Inactive to TXE#
T12 TXE# Inactive After WR Cycle
*Load = 30pF
Rev. 1.0 (November 2008)
T3
R I P T I O N
R I P T I O N
T9
R R I I P P T T I I O O N N
T5
T1
Valid data
M
M
50
50 + T6
20
0
0
80
T11
T7
Valid data
M M
50
50
20
0
5
80
4
T6
T2
T4
I N M A X U
I N M A X
-
-
50
-
25
-
T12
T8
T10
I I N N M M A A X X U
-
-
-
-
25
-
© DLP Design, Inc.
N I T
U N I T
nS
nS
nS
nS
nS
nS
U N N I I T T
nS
nS
nS
nS
nS
nS