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The DLP-USB245R is DLP Design's smallest USB-to-parallel FIFO interface module and
utilizes the popular FT245R IC with FTDIChip-ID™ feature from FTDI. In addition to enabling
standard USB-to-FIFO designs, both asynchronous and synchronous bit-bang interface modes
are also available.
The DLP-USB245R is available in a lead-free, RoHS-compliant, compact 18-pin, 0.1-inch
standard DIP footprint.
FEATURES:
• Single-chip USB-to-parallel FIFO bidirectional data-transfer interface.
• Entire USB protocol handled on the FT245R; no USB-specific firmware programming is
required.
• Fully integrated 1024-bit EEPROM storing device descriptors and FIFO I/O configuration.
• Data transfer rates up to 1Mbyte per second.
• 256-byte receive buffer and 128-byte transmit buffer utilizing buffer-smoothing technology to
allow for high data throughput.
• FTDI's royalty-free Virtual COM Port (VCP) and direct (D2XX) drivers eliminate the requirement
for USB driver development in most cases.
• Unique USB FTDIChip-ID™ feature.
• Configurable FIFO interface I/O pins.
• Synchronous and asynchronous bit-bang interface options with RD# and WR# strobes.
• Device supplied preprogrammed with a unique USB serial number.
• Supports bus-powered, self-powered and high-power bus-powered USB configurations.
• Integrated level converter on FIFO interface for connection to external logic running at between
+1.8V and +5V.
• True 5V/3.3V/2.8V/1.8V CMOS drive output and TTL input.
• Configurable I/O pin output drive strength.
• Integrated power-on-reset circuit.
• Fully integrated power-supply filtering; no external filtering is required.
• +3.3V to +5.25V single-supply operation.
• Low operating and USB Suspend current.
• UHCI/OHCI/EHCI host-controller compatible.
• USB 2.0 full-speed compatible.
• -40°C to 85°C extended operating temperature range.
Rev. 1.0 (November 2008)
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Related Manuals for DLP Design USB-Parallel FIFO Module DLP-USB245R
Summary of Contents for DLP Design USB-Parallel FIFO Module DLP-USB245R
- Page 1 LEAD-FREE The DLP-USB245R is DLP Design’s smallest USB-to-parallel FIFO interface module and utilizes the popular FT245R IC with FTDIChip-ID™ feature from FTDI. In addition to enabling standard USB-to-FIFO designs, both asynchronous and synchronous bit-bang interface modes are also available. The DLP-USB245R is available in a lead-free, RoHS-compliant, compact 18-pin, 0.1-inch standard DIP footprint.
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Page 2: Application Areas
• Windows CE 4.2, 5.0 and 6.0 • Linux 2.4 and greater The drivers listed above are all available for free download from the DLP Design website www.dlpdesign.com and FTDI website www.ftdichip.com. Various third-party drivers are also available for other operating systems; see the FTDI website www.ftdichip.com for details. -
Page 3: Absolute Maximum Ratings
Commands to set the baud rate are ignored; the device always transfers data at its fastest rate regardless of the application’s baud-rate setting. The latest versions of the drivers are available for download from DLP Design’s website at www.dlpdesign.com. Rev. 1.0 (November 2008) -
Page 4: Timing Diagrams
WR Active Pulse Width WR to WR Pre-Charge Time Valid Data Setup to WR Falling Edge* Valid Data Hold Time from WR Inactive* WR Inactive to TXE# TXE# Inactive After WR Cycle *Load = 30pF Rev. 1.0 (November 2008) © DLP Design, Inc. -
Page 5: Application Notes
FT_EE_UARead is used to read its contents. Download FTDI Application Notes AN_103 and AN_104 for detailed instructions on how to install the drivers on XP and Vista platforms. Rev. 1.0 (November 2008) © DLP Design, Inc. -
Page 6: Pinout Description
PC is not read from the FT245R device by an attached microcontroller, microprocessor, DSP, FPGA, ASIC, etc. 7.0 PINOUT DESCRIPTION Pin 18 Pin 1 Pin 10 Pin 9 Top View (Interface Headers on bottom of PCB) Rev. 1.0 (November 2008) © DLP Design, Inc. - Page 7 20ms which will cause the device to request a resume on the USB bus. DB1 - FIFO Data Bus Bit 1 DB4 - FIFO Data Bus Bit 4 DB0 - FIFO Data Bus Bit 0 Rev. 1.0 (November 2008) © DLP Design, Inc.
- Page 8 EEPROM of the FT245R should be programmed to match the total current drawn by the target system. Note: If using PWREN# (available using the CBUS), the I/O pin should be pulled to VCCIO using a 10k-ohm resistor. Rev. 1.0 (November 2008) © DLP Design, Inc.
- Page 9 Figure 3 shows how to configure the DLP-USB245R to interface with a 3.3V logic device. In this example, the target electronics provide the 3.3 volts via the VCCIO line (Pin 7) which, in turn, will cause the FT245R interface I/O pins to drive out at the 3.3V level. Rev. 1.0 (November 2008) © DLP Design, Inc.
- Page 10 FT245R EEPROM to inform the system of its power requirements. 4. PWREN# gets its VCC from VCCIO. For designs using 3.3-volt logic, ensure that VCCIO is not powered down during Suspend. Rev. 1.0 (November 2008) © DLP Design, Inc.
- Page 11 This product and its documentation are supplied on an as-is basis, and no warranty as to their suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory rights are not affected.
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Page 12: Contact Information
This document provides preliminary information that may be subject to change without notice. 12.0 CONTACT INFORMATION DLP Design, Inc. 1605 Roma Lane Allen, TX 75013 Phone: 469-964-8027 Fax: 415-901-4859 Email Sales: sales@dlpdesign.com Email Support: support@dlpdesign.com Website URL: http://www.dlpdesign.com Rev. 1.0 (November 2008) © DLP Design, Inc. - Page 13 AGND TEST VCCIO...
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