Appendix D. Post Code Definition - Abit Socket 462 System Board User Manual

POST Code Definition

Appendix D. POST Code Definition

AWARD POST Code Definition:
Code Description
CF Test CMOS R/W functionality
Early chipset initialization:
-Disable shadow RAM
C0
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
Detect memory
C1 -Auto-detection of DRAM size, type and ECC
-Auto-detection of L2 cache (socket 7 or below)
C3 Expand compressed BIOS code to DRAM
C5 Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01 Expand the Xgroup codes locating in physical address 1000:0
03 Initial Superio_Early_Init switch
1. Blank out screen
05
2. Clear CMOS error flag
1. Clear 8042 interface
07
2. Initialize 8042 self-test
1. Test special keyboard controller for Winbond 977 series Super I/O chips
08
2. Enable keyboard interface
1. Disable PS/2 mouse interface (optional)
0A 2. Auto detect ports for keyboard & mouse followed by a port & interface swap (optional)
3. Reset keyboard for Winbond 977 series Super I/O chips
Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep
0E
beeping the speaker
Auto detect flash type to load appropriate flash R/W codes into the run time area in F000
10
for ESCD & DMI support
Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time
12
clock power status, and then check for override
Program chipset default values into chipset. Chipset default values are MODBINable by
14
OEM customers
Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also
16
POST 26.
Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU level (586
18
or 686)
Initial interrupts vector table. If no special specified, all H/W interrupts are directed to
1B
SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR.
1D Initial EARLY_PM_INIT switch
1F Load keyboard matrix (notebook platform)
21 HPM initialization (notebook platform)
1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute.
23 2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value
instead.
Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration
24
of the ESCD's legacy information.
D-1
User's Manual