Sdram Cycle Length; Video Bios Cacheable - TYAN Trinity 100AT S1590 User Manual

Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing

SDRAM Cycle Length

DRAM Read Pipeline
Cache Rd+CPU Wt Pipeline
Cache Timing

Video BIOS Cacheable

System BIOS Cacheable
Memory Hole At 15Mb Addr
AGP Aperture Size
Bank 0/1, 2/3, 4/5 DRAM Timing
The system board designer must select the proper value for these fields,
according to the specifications of the installed DRAM chips. Turbo mode
reduces CAS access time by 1 clock tick.
SDRAM Cycle Length
This field sets the CAS latency timing.
DRAM Read Pipeline
Select Enabled to pipeline reads from system memory. Pipelining improves
system performance.
Cache Rd+CPU Wt Pipeline
Select Enabled to pipeline reads from cache memory and writes from the CPU.
Pipelining improves system performance.
Cache Timing
For a secondary cache of one bank, select Faster. For a secondary cache of
two banks, select Fastest.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
S1590 Trinity 100AT
ROM PCI/ISA BIOS (2A5LET59)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: FP/EDO 70ns
: FP/EDO 70ns
: SDRAM 10ns
: 2
: Disabled
: Disabled
: Fast
: Disabled
: Disabled
: Disabled
: 64M
45
OnChip USB
USB Keyboard Support
CPU Warning Temperature : Disabled
Current CPU Temperature : 61C/141F
Current CPUFAN1 Speed
Current CPUFAN2 Speed
Current Vin3(V)
ESC : Quit -¯ ®¬
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
: Disabled
: Disabled
: 0RPM
: 0RPM
: 2.45V
: Select Item