Port 80H Post Codes - Intel BOXDP55SB Product Manual

Intel Desktop Board DP55SB Product Guide
Table 17 lists the Port 80h POST codes in hexadecimal notation.
Table 17. Port 80h POST Codes
POST Code
00
01-05
10, 20, 30,
40, 50
08
09
0A, 0B
0C
0D
0E
0F
11
12
13
14
15
16
17, 18
19, 1A
1B, 1C
21
23
24
27
28
29
2A, 2B
31, 33, 34
76
Description
ACPI S States
Entering S0 state, standard
Entering S1-S5 state
Resuming from S1-S5 state
Security Phase (SEC)
Starting BIOS execution after CPU BIST
SPI prefetching and caching
Load BSP/APS microcode
Platform program base addresses
Wake up all APS
Initialize NEM
Pass entry point of the PEI core
PEI Phase Before MRC
Set bootmode, GPIO init
Early chipset register programming
Basic PCH init, discrete device init
LAN init
Exit early platform init driver
SMBUS driver init
Entry/Exit to SMBUS execute read/write
Entry/Exit to CK505 programming
Entry/Exit to PEI overclock programming
MEC Memory Detection
MRC entry point
Reading SPD from memory DIMMs
Detecting presence of memory DIMMs
Configuring memory
Testing memory
Exit MRC driver
PEI After MRC
Start/finish programming MTRR settings
PEIMs/Recovery
Recovery has initiate, load, valid