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Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
Configuration options: [Disabled] [Enabled]
The following sub-items appear when this item is Disabled.
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [5 Clocks] [4 Clocks] [3 Clocks] [6 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks] [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2 Clocks] [3 Clocks]
[4 Clocks] [5 Clocks] [6 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Configuration options: [4 Clocks] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clocks]
Sets the DRAM write recovery time.
Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks]
[6 Clocks]
Graphic Adapter Priority [PCI Express/Int-VGA]
Allows selection of the graphics controller to use as a primary boot device.
Configuration options: [Internal VGA] [PCI Express/Int-VGA] [PCI Express/
PCI] [PCI/PCI Express] [PCI/Int-VGA]
Onboard LAN Boot ROM [Disabled]
Allows you to enable or disable the onboard LAN boot ROM.
Configuration options: [Disabled] [Enabled]
PEG Port [Enabled]
Allows you to enable or disable the PCI Express Graphics port.
Configuration options: [Disabled] [Enabled]
PEG Port VC1 Map [TC7]
Allows you to disable or set the PCI Express Graphics port VC1 map.
Configuration options: [Disabled] [TC1] ~ [TC7]
PEG Force x1 [Disabled]
Configuration options: [Disabled] [Enabled]
ASUS P5LD-MR
4-23
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