Init Signal Input Circuit - Epson LQ-510 Technical Manual

PRINCIPLES OF OPERATION
Reset Caused by CPU
A LOW signal from CPU port PB6 passes through the low-pass filter formed by R64 and C40 and inputs
to pin 47 of the IC7A gate array. In the array, waveform shaping occurs and causes the DISC terminal to
go LOW; the charge on capacitance C19 is then released, and terminal THLD of the gate array goes LOW.
The reset signal is then output by the ROUT terminal.
INIT Signal Input (from CN1 or CN2)
When the INIT signal is input from either the host interface or optional interface, the CPU performs initial-
ization. From the interface, the INIT signal passes through the low-pass filter formed by R62 and C9 and
inputs to the NMI offering terminal of the CPU. The NMI offering terminal will also input the voltage of the
+24 VDC line formed by Zener diode ZD2 and transistor Q32.
ZD2
M A 4 1 6 0
1 . 6 K
2-32
C42
4 7 0 P
+ 2 4 V
10k
R17
G
P
Figure 2-39. INIT Signal Input Circuit
R96
2 2 0 K
C 1 6
CPU
REV.-A
LQ-510