Epson LQ-510 Technical Manual page 199

REV.-A
Pins
Signal
1-8 PA0-7
9-16 PB0-7
17-24 PC0-7
25 NMI
26 INT 1
27, 29 MODE1,0
28 RESET
30, 31
X2, X1
32
Vss
33 AVss
34-41 AN0-7
42 VAref
43
AVcc
44 RD
45
WR
46 ALE
47-54 PF0-7
55-62 PD0-7
63
V
D D
64
Vcc
LQ-510
Table A-5. µPD7810/7811 Port Functions
Direction
Port A: 8-bit l/O with output latch. l/O possible with mode A
In/Out
(MA) register. Output HIGH.
In/Out Port B: 8-bit I/O with output latch. l/O possible with mode B
(MB) register. Output HIGH.
In/Out Port C: 8-bit l/O with output latch. Port control mode can be
set by mode control C (MCC) register. Output HIGH.
In Non-maskable interrupt of the edge trigger (trailing edge).
In Maskable interrupt input of the edge trigger (leading edge).
Also used as the AC input zero cross detecting terminal.
7611: 0 = LOW and 1 = HIGH.
In/Out
7810 modes set according to external memory (see Table A-2).
In LOW reset.
-
Crystal connection for built-in clock pulse. When clock pulses
are supplied externally, input must be to Xl.
-
Supply voltage, Vss, 0V.
-
Analog Vss.
In 8 analog inputs of the A/D converter. AN7-4 can be used as
the input terminals to detect the leading edge and to set the
test flag upon detection of the trailing edge.
In
Reference voltage.
-
Analog Vcc.
out Read strobe. LOW at the read machine cycle and at reset,
HIGH at other times.
out Write strobe. LOW during the write machine cycle and at reset,
HIGH at other times.
out Address latch enable. Latches the lower B address bits to ac-
cess external memory.
Port F:
7611: Port bit-by-bit l/O possible by mode F register. In exten-
sion mode gradual address output assignment is possible in
accordance with the size of external memory. See Table A-3.
7810: By setting mode 0 and 1, assignment to the address bus
(AB15-8) can be made in accordance with the size of the exter-
nal memory. The remaining terminals can be used as l/O
ports. See Table A-4.
Port D:
7811: Port bit-by-bit l/O possible. In extension mode, PD7-0
acts as the multiplexed address/data bus (AD7-0).
7810: Multiplexed address/data bus to access external
memory.
- Supply voltage, V
-
Supply voltage, VCC +5 V.
Descriptions
+5 V.
DD
APPENDIX
A-5