Epson LQ-570 Service Manual page 23

REV.-A
Table 2-5. Functions of the Main IC and Circuits (Cont.)
Location
PROM
MROM
(Mask ROM)
HEAD GATE
ARRAY
. . .
Vref Circuit
2.3.2 Reset Circuit
Figure 2-19 shows the reset circuit block diagram. The reset circuit issues the /RESET signal. Each
part of the control cimuits is initialized when this /RESET signal is received. The renditions when the
/RESET signal is output are described below.
When Turning on the Power Supply
Immediately after the power has been turned on, PST 529 (IC19) outputs the /PON pulse. E05A50
then outputs the /RESET signal from the /OUT port of IC19. After a certain time has elapsed, the
charge in the condenser builds up again. The M-ILD signal is canceled and then the /RESET signal
is canceled.
Resets performed by the CPU itself (CPU
The CPU outputs the /RESET signal if there is a /RESET request for E05A50 and E05A50 output the
/DISC pulse. "
IOUT
+5
PROM contains the program that runs the CPU.
Holds the CPU working area and the various buffers. (1E is not used for an 80-
column device and is not installed.)
Holds the character design (also called the character generator).
information as the TOF position.
This is a gate array mnsisting of three components configured on a single chip:
Mode 1: HD1+HD2+HD3+......+HD22+HD23+HD24
Mode 2: HD24+HD23+HD22+...... +HD3+HD2+HD1
Delay control(for low noise)
Image data latching
This is a circuit for generating the reference voltage used in the A/D mnvertor
within the CPU.
self-reset)
I
Figure 2-19. Reset Circuit Block Diagram
2-15
Functions
E05A50(IC11)
107
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