TYAN Tomcat K8E-SLI S2866 User Manual page 55

3.8.1 DRAM Configuration
Timing Mode
x Memclock index value (Mhz)
x CAS# latency (Tel)
S/W memory hole Romapping
H/W memory hole Remapping
MTRR mapping mode
DRAM ECC feature control
ECC memory Interlock
ECC MCE enable
Chip-Kill mode enable
ECC Redirection
DRAM background scrubber
L2 cache background scrub
DCache background scrubber
Timing Mode
This option permits you to either manually select memory timings, or allow
the SPD (Serial Presence Detect) to determine the said timings automatically.
Auto / Manual
Memclock index value (Mhz)
This feature is used to set the Memclock index value.
100Mhz / 133Mhz / 166Mhz / 200Mhz
CAS# latency (Tel)
This setting controls the time delay (in clock cycles - CLKs) that passes
before the DRAM starts to carry out a read command after receiving it. This
also determines the number of CLKs for the completion of the first part of a
burst transfer. In other words, the lower the latency, the faster the
transaction.
2 / 2.5 / 3
S/W Memory Hole Remapping
This feature is used to configure the function of S/W memory hole remapping.
Enabled / Disabled
Phoenix-AwardBIOS CMOS Setup Utility
DRAM Configuration
[Auto]
200Mhz
2.5
[Enabled]
[Disabled]
[Continuous]
[Enabled]
[At Least One]
[Enabled]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[Disabled]
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