Acer Extensa 900 Series Maintenance Manual page 66

One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/
writes. One 32-bit wide posted-write buffer is provided for PCI memory write cycles to
the ISA bus. It also supports a PCI to ISA IRQ routing table and level-to-edge trigger
transfer.
The chip has two extra IRQ lines and one programmable chip select for motherboard
Plug-and-Play functions. The interrupt lines can be routed to any of the available ISA
interrupts.
The on-chip IDE controller supports two IDE connectors for up to four IDE devices
providing an interface for IDE hard disks and CD-ROMs. The ATA bus pins are dedicated
to improve the performance of IDE master.
The M1523 supports the Super Green feature for Intel and Intel compatible CPUs. It
implements programmable hardware events, software event and external switches (for
suspend/turbo/ring-in). The M1523 provides CPU clock control (STPCLKJ). The
STPCLKJ can be active (low) or inactive (high) in turn by throttling control.
4.2.3.2.1 M1523 Features Summary
Provides a bridge between the PCI bus and ISA bus
PCI interface
Supports PCI master and slave interface
Supports PCI master and slave initiated termination
PCI spec. 2.1 compliant (delay transaction support)
Buffers
8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI
bus
32-bit posted-write buffer for PCI memory write and I/O data write (for sound
card) to ISA bus
Provides steerable PCI interrupts for PnP PCI devices
Up to eight PCI interrupts routing
Level-to-edge trigger transfer
Enhanced DMA controller
Provides seven programmable channels (four for 8-bit data size, three for
16-bit data size)
32-bit addressability
Provides compatible DMA transfers
4-10 Theory of Operation