Memory Channel Interleaving; I/O Technologies; Pci Express Technology - HP DL370 - ProLiant - G6 Performance Introduction Manual

Memory channel interleaving

The Xeon 5500 Series processor retrieves data from the memory DIMMs in 64-byte chunks. With
channel interleaving, the system is set up so that each consecutive 64-byte chunk in the memory map
is physically transferred by means of alternate routing through the three available data channels.
The result is that when the memory controller needs to access a block of physically contiguous
memory, the requests are distributed more evenly across the three channels rather than potentially
stacking up in the request queue of a single channel. This alternate routing decreases memory access
latency and increases performance. Memory channel interleaving, does, however, increase the
probability that more DIMMs need to be kept in an active state (requiring more power) since the
memory controller alternates between channels and therefore between DIMMs. This is discussed
further in the "Power and thermal technologies" section.
For additional information about DDR-3 memory, see the paper titled "Memory technology evolution:
an overview of system memory technologies" at
http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf

I/O technologies

ProLiant 300-series G6 servers incorporate PCI Express, Serial-Attached SCSI (SAS), and Serial ATA
(SATA) I/O technologies. PCI Express lets administrators add expansion cards with various
capabilities to the system. SAS is a serial communication protocol for direct attached storage devices
such as SAS and SATA hard drives.

PCI Express technology

All ProLiant G6 servers support the PCIe 2.0 specification. PCIe 2.0 has a per-lane signaling rate of
5 Gb/s ―double the per-lane signaling rate of PCIe 1.0 (Figure 4).
Figure 4. PCIe data transfer rates
Lane 1 Send Lane 1 Send
Lane 1 Receive Lane 1 Receive
Source Source
n n
Lane Lane Send Send
n n
Lane Lane Receive Receive
PCIe 2.0 is completely backward compatible with PCIe 1.0. A PCIe 2.0 device can be used in a PCIe
1.0 slot and a PCIe 1.0 device can be used in a PCIe 2.0 slot. Table 2 shows the level of
interoperability between PCIe cards and PCIe slots.
Max. bandwidth
(Send or receive)
Link
size
PCIe 1.0
x1 250 MB/s
Target Target
x4 1 GB/s
x8 2 GB/s
x16 4 GB/s
Total
(Send and receive)
PCIe 2.0 PCIe 1.0
500 MB/s 500 MB/s
2 GB/s 2 GB/s
4 GB/s 4 GB/s
8 GB/s 8 GB/s
.
PCIe 2.0
1 GB/s
4 GB/s
8 GB/s
16 GB/s
9