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HP 226824-001 - ProLiant - ML750 Introduction Manual

Fully-buffered dimm technology
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Download this manual See also: Troubleshooting Manual, Introduction Manual
Fully-Buffered DIMM technology in HP ProLiant servers
technology brief
Abstract.............................................................................................................................................. 2
Introduction......................................................................................................................................... 2
Performance barriers for traditional DIMM.............................................................................................. 2
Fully-Buffered DIMM architecture ........................................................................................................... 4
Benefits........................................................................................................................................... 6
Simplified board design ................................................................................................................ 6
Higher memory capacity ............................................................................................................... 6
Higher performance...................................................................................................................... 7
Improved reliability....................................................................................................................... 7
Challenges ...................................................................................................................................... 8
Latency ....................................................................................................................................... 8
Power and thermal loads............................................................................................................... 8
Performance tuning, achieving maximum performance ............................................................................. 9
Conclusion.......................................................................................................................................... 9
For more information.......................................................................................................................... 10
Call to action .................................................................................................................................... 10

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  Summary of Contents for HP 226824-001 - ProLiant - ML750

  • Page 1: Table Of Contents

    Fully-Buffered DIMM technology in HP ProLiant servers technology brief Abstract.............................. 2 Introduction............................2 Performance barriers for traditional DIMM....................2 Fully-Buffered DIMM architecture ......................4 Benefits............................6 Simplified board design ........................ 6 Higher memory capacity ....................... 6 Higher performance........................7 Improved reliability........................7 Challenges ............................

  • Page 2: Abstract

    Abstract This paper describes the features, benefits, and challenges of Fully-Buffered dual inline memory module (FB-DIMM) technology. It also provides rules for populating FB-DIMM slots to achieve maximum performance in HP ProLiant servers. Introduction HP ProLiant servers provide balanced system architectures that deliver peak performance per watt of power.
  • Page 3 Each stub-bus connection creates an impedance discontinuity that negatively affects signal integrity. In addition, each DIMM creates an electrical load on the bus. The electrical load accumulates as DIMMs are added. These factors decrease the number DIMMs per channel that can be supported as the bus speed increases.

  • Page 4: Fully-Buffered Dimm Architecture

    Fully-Buffered DIMM architecture The FB-DIMM architecture has serial links between the memory controller and the FB-DIMMs, which are connected in a daisy chain configuration (Figure 3). Relative to the memory controller, there are 10 outbound links and 14 inbound links, also known as southbound and northbound links, respectively.
  • Page 5 The AMB is an intelligent chip that manages serial communication with the memory controller and parallel communication with local DRAM devices (Figure 4). Each AMB receives signals (address, write data, and command information) through the outbound links and re-transmits the signal to the next FB-DIMM on the channel.

  • Page 6: Benefits

    Benefits The benefits of FB-DIMM architecture include • Simplified board design • Higher memory capacity • Higher performance • Improved reliability Simplified board design FB-DIMMs use a 240-pin socket similar to that used for traditional DDR2 registered DIMMs; however, FB-DIMMs require significantly fewer signal traces. FB-DIMMs have 69 signal traces compared to 138 traces for DDR2 registered DIMMs.

  • Page 7: Higher Performance

    Higher performance The asynchronous serial links between the memory controller and AMB enable higher performance by the memory subsystem. The two devices operate on independent clocks, so the transmitting device embeds a bit clock with the data stream. The bit clock consists of a start bit that indicates the beginning of a chunk of information, or data word, and a stop bit that indicates the end of the data word.

  • Page 8: Challenges

    Challenges The challenges for the FB-DIMM architecture include latency as well as power and thermal load. Latency The FB-DIMM architecture adds two types of latency, serialization latency and transmission latency. Serialization latency occurs when data is processed by the AMB; therefore, it is necessary. Transmission latency is measured from the time a read request is initiated to the time the memory controller receives the first frame of read data.

  • Page 9: Performance Tuning, Achieving Maximum Performance

    Performance tuning, achieving maximum performance HP ProLiant servers implement a multi-branch memory architecture to reduce latency and enhance performance. This architecture allows the memory controller to fetch data in parallel from the different channels through memory interleaving. The latency for two channels is almost 40 percent lower than that of a single channel.

  • Page 10: For More Information

    For more information For additional information, refer to the resources listed below. Source Resource Hyperlink JEDEC Web site http://www.jedec.org HP Advanced http://h18004.www1.hp.com/products/servers/technology/whitepapers/adv- Memory Protection technology.html Memory http://h18004.www1.hp.com/products/servers/technology/whitepapers/adv- technology technology.html evolution Call to action Send comments about this paper to TechCom@HP.com. ©...

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