Lenovo Ispirati 2001 User Manual page 39

4-8
SDRAM Cycle
Time Tras/Trc
SDRAM
RAS-to-CAS
Delay
SDRAM RAS
Precharge Time
System BIOS
Cacheable
Video BIOS
Cacheable
Memory Hole At
15M-16M
CPU Latency
Timer
Delayed
Transaction
OnChip Video
Window Size
Local Memory
Frequency
Initial Display
Cache
CAS# Latency
Paging Mode
Control
RAS-to-CAS
Override
RAS# Timing
RAS# Precharge
Timing
Item Options
5/7
6/8
3
2
3
2
Enabled
Disabled
Disabled
15M-16M
Enabled
Disabled
Enabled
Disabled
--
100Mhz
133MHz
Enabled
Disabled
2
3
Close
Open
By CAS# LT
Override(2)
Slow
Fast
Slow Fast
Chapter 4: BIOS Setup
Description
Specifies the timing spec of
SDRAM.
This item specifies the length of
the delay inserted between
RAS(Row Address Strobe)and
CAS(Column Address Strobe)
signal of the DRAM system
memory access cycle.
This item specifies the length of
the RAS precharge part of the
DRAM system memory access
cycle when synchronous DRAM
system memory is installed in the
computer.
If cache controller is enabled,
enabling these causes video BIOS
cache at C0000H-C7FFFH or
system BIOS ROM at
F0000H-FFFFFH to be cached for
faster execution.
'Enabled' makes 15M-16M area
reserved for ISA use. (Some ISA
cards may require specific areas
of memory in order to function.)
Enables or disables this feature.
Selects ISA device speed.
'Enabled' is for slow speed ISA
device in system.
Displays the window size of video
controller.
Sets display cache at 100Mhz or
133MHz.
The onboard video includes a
4MB onboard display cache.
'Enabled' utilizes this cache.
This item regulates the column
address strobe.
Sets the Paging mode control
when 'Initial Display Cache' is
enabled.
Specifies the interval between
refresh signals to DRAM system
memory when 'Initial Display
Cache' is enabled.
Regulates the speed of row
address strobe when 'Initial
Display Cache' is enabled.
Sets the precharge timing of row
address strobe when 'Initial
Display Cache' is enabled.