Timing Sequence For 8 Bit Parallel Interface; Timing Sequence For 4 Bit Parallel Interface; Industrial Electronic Engineers, Inc; Van Nuys, California - IEE 03875-06-0114 Reference Manual

4.5

Timing Sequence for 8 Bit Parallel Interface

Figure 13 illustrates the typical Busy Flag check sequence for an 8 bit data interface.
RS
R/W
E
Internal
DB7
Instruction
Figure 13
4.6

Timing Sequence for 4 Bit Parallel Interface

Figure 14 illustrates the typical Busy Flag check sequence for a 4 bit data bus interface.
RS
E
DB IR
7
Instruction
Write
Figure 14
Note: IR , IR :
7 3
AC :
3

Industrial Electronic Engineers, Inc.

Van Nuys, California

Internal Operation
Data Busy
Busy Flag
Write Check
Busy Flag Check Sequence for 8–bit Parallel Interface
Internal Operation
IR
Busy
7 3
Busy Flag
Check
Busy Flag Check Sequence for 4–bit Parallel Interface
Instruction, 7th bit & 3rd bit
Address Counter, 3rd bit
Busy
Busy Flag
Check
Not
AC AC
Busy
3
Busy Flag
Check
SIZE CODE IDENT
A NO.
05464
Scale: NONE
Not
Busy
Busy Flag
Check
D IR
3 7 3
Instruction
Write
S03875–06–0114
Rev A Sheet 15
IR 7
Instruction
Write