Table Of Contents - Dell PowerEdge 3250 Product Manual

Intel® Server Platform SR870BH2

Table of Contents

1. Introduction .......................................................................................................................... 1
2. SEL Overview ....................................................................................................................... 2
3. EFI-Based SELViewer Task ................................................................................................. 3
4. SR870BH2 SEL Data Tables ................................................................................................ 4
5. SR870BH2 Machine Check Error Handling ........................................................................ 7
5.1 Classification of Errors..................................................................................................... 7
5.2 Error Types ...................................................................................................................... 7
5.3 Error Signaling ................................................................................................................. 8
5.4 Error Reporting ................................................................................................................ 9
5.5 Thresholding .................................................................................................................. 10
5.6 SEL Event Log Format for Machine Check Errors......................................................... 10
6. SR870BH2 PCI Device IDs ................................................................................................. 12
7. BIOS POST Error Codes and Messages........................................................................... 13
7.1 Error Code Classification ............................................................................................... 13
8. Debug Methodology and Failure Isolation ....................................................................... 18
8.1 Memory.......................................................................................................................... 18
8.1.1 Memory Debug Methodology ................................................................................... 18
8.1.2 Memory Component Isolation .................................................................................. 18
8.2 Processor....................................................................................................................... 19
8.2.1 Processor Debug Methodology................................................................................ 19
8.2.2 Processor Component Isolation ............................................................................... 19
8.3 Processor - Late Self-test .............................................................................................. 20
8.3.1 Late Self-test Display ............................................................................................... 20
8.3.2 Late Self-test Usage Notes ...................................................................................... 21
8.4 Watch Dog Timer........................................................................................................... 21
8.4.1 Watch dog timer Debug Methodology...................................................................... 21
8.4.2 Watchdog Timer Failure Isolation ............................................................................ 21
8.5 Fault Resilient Boot (FRB) ............................................................................................. 21
8.5.1 FRB3 - BSP Reset Failures..................................................................................... 22
8.5.2 FRB2 - BSP POST Failures .................................................................................... 22
8.5.3 FRB1 - BSP Self-Test Failures................................................................................ 22
8.5.4 FRB Debug Methodology......................................................................................... 22
Revision 1.1
Table of Contents
iii